System for processing a digital image using two or more defined regions

ABSTRACT

System for processing a digital image using multiple regions where each of the multiple regions is defined using a portion of the digital image. In addition, a top margin, a bottom margin, a left margin, and a right margin are defined to include margin pixels for each of the multiple regions of the digital image. Margin pixels are defined as neighboring pixels for a region of the digital image and may contain pixels that are part of the digital image, part of the region of the digital image, and/or newly generated pixels. Various techniques such as on the fly generation or using a predetermined process for video data information generation, such as replication or using a fixed color, may be used to generate the margin pixels. Each of the multiple regions is processed with its margin pixels to create a new quadrilateral digital image that is completely processed and/or scaled. The appropriate portion of the processed quadrilateral digital image is displayed using a display region of an electronic display panel having multiple display regions. The concatenation of the displayed portions of the processed quadrilateral digital images produces the original digital image using the electronic display panel.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.12/800,266, filed May 12, 2010, entitled “Apparatus For Partitioning andProcessing A Digital Image Using Two Or More Defined Regions”, which isa continuation-in-part of U.S. patent application Ser. No. 12/655,769,filed Jan. 6, 2010, entitled “Method For Partitioning A Digital ImageUsing Two Or More Defined Regions”, both applications are incorporatedby reference herein in their entirety.

TECHNICAL FIELD

The subject of this application generally relates to the field ofdigital image processing and more particularly to digital image scalingfrom an original image size to a target image size.

BACKGROUND

Traditional cameras are used to take photographs by capturing light ontophotographic films. Digital cameras use electronic devices such asCharge Coupled Devices (CCD) to capture light, of an original image, andproduce a digital representation of an image. The digital representationcan be further manipulated using different compression or transmissiontechniques or standards such as Moving Picture Experts Group (MPEG).Furthermore, the digital representation of the image can be stored invarious digital formats in accordance with the intended memory storagemediums e.g. Hard disk, DVD, CD-Rom, etc. . . . such that thereproduction of the original image may be achieved using a variety ofmeans or mediums using the stored digital representation of the originalimage. For examples, electronic display devices can display the image ontheir screen.

The digital representation of the image can greatly vary in qualitydepending on the sampling of the original image. Each sample of theoriginal image represents a small portion of the overall image.Therefore, more samples are required in order to have a better or moreaccurate representation of the original image. A pixel represents onesample of the original image. Normally, an image is sampled using atwo-dimensional grid having a width, X, and a height, Y, that arespecified in unit of pixel, where the digital image resolutioncorresponds to X time Y, and each pixel corresponds to the smallestsingle component of the original image. For example, a first camera witha resolution of 640×480 would have 640 pixels in the horizontaldirection and 480 pixels in the vertical direction. The digital imageresolution, total number of pixels, is 307,200 pixels. Higher resolutionrequires more pixels to be generated when capturing an image, and thecloser the digital image produced is to the original image. Hence, asecond digital camera with a resolution of 1280×960 would have a totalnumber of pixels of 1,228,800 pixels or four times the resolution of thefirst camera.

Each pixel of a digital image corresponds to data information that isexpressed as a number of bits that is used to describe each pixel (orsample) of the original image. This data information is normallyexpressed as number of bits per pixel (bpp). A broader range of distinctcolors can be represented with a higher number of bits per pixel.Nowadays, There are many different formats that are in use to captureand/or display color information, e.g. the RGB. For example, a 24-bitcolor model uses 8 bits to represent red, 8 bits to represent blue and 8bits to represent green. Under this model, each of these three colorspossesses a 2⁸ or 256 levels. Therefore, they can be combined(256×256×256) to give a possible 16,777,216 colors.

A video camera captures a scene for a specific duration of time, andproduces many sequential digital images. Normally, each digital image isreferred to as a frame, having a frame size defined as number ofhorizontal pixels×number of vertical pixels. A frame rate is alsospecified that represents the number of frames being captured persecond. In addition, a scanning system is identified as progressive orinterlaced to indicate how the video frames are generated and thus howthey should be processed and displayed so that the original scene isfaithfully reproduced when these digital images are played back insequence, e.g. using an electronic display panel or a digital televisionset.

In order to reproduce the original scene timing, each digital image, orframe within the scene, must be reproduced and displayed in a givenamount of time. Hence, the time required to process and display onepixel is limited and finite. Electronic display devices resolution isspecified, in a similar way as explained above for a digital camera, ashaving X by Y pixels. Again, the higher the resolution of the electronicdisplay device is, the better the image that is being reproduced. As theelectronic display panel technology advances to an ever-higherresolution, a bigger challenge to the device electronics is to be ableto process data information for each pixel within an ever-smaller amountof time.

The processing demands on electronic circuits for High-Definitiontelevision (HD TV), e.g. 1,920 pixels wide and 1,080 pixels high, ismuch greater than a Standard-Definition television (SD TV), e.g. 720pixels wide and 480 pixels high. The next generation of digital TVs andprojectors, recently developed, will be able to display four times thehigh definition resolution of current HD TV sets. This Quad-HD set iscapable of displaying 3,840 pixels wide and 2,160 pixels high. Thispresents a big challenge to the processing circuitry, where each pixelmust be processed and faithfully reproduced regardless of the inputimage resolution having a Quad-HD content from standardized interfacessuch as HDMI 1.4 or DisplayPort 1.2a and/or other lower resolution suchas 1,920×1,080 or lower.

The need arises to provide an electronic system capable of faithfullyprocessing digital images with various resolutions and display themusing a Quad-HD resolution display or higher resolution type ofelectronic display panels. Marseille Networks' 4×HD™ video technologydelivers the ability to process digital images to be displayed in3840×2160 resolution, while selectively removing artifacts andpreserving stunning image details. Furthermore, Marseille Networks isthe first to introduce Quad-HD solution to home theater systems.Marseille Networks' 4×HD™ video technology provide an efficient systemwith ample flexibility and processing power for blending and or scalingvarious types of video image streams, including High-Definition streams,to be displayed over Quad-HD display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary model of a digital image using pixels arrangedas a two-dimensional grid format.

FIG. 2A shows another exemplary model of a digital image, where a firstregion that corresponds to a quadrangle digital image is defined withinthe digital image.

FIG. 2B shows another exemplary model of a digital image, where a secondregion, which comprises the first region, is defined within the digitalimage and corresponds to a quadrilateral digital image, in accordancewith one embodiment.

FIG. 3A shows an exemplary model of a quadrilateral digital image thatcomprises a quadrangle digital image surrounded by margin pixels, inaccordance with another embodiment.

FIG. 3B shows an exemplary model of a quadrilateral digital image ofFIG. 3A that is centered within the edges of a digital image, inaccordance with another embodiment.

FIG. 3C shows an exemplary model of a quadrilateral digital image ofFIG. 3A that is located at the top-left corner of a digital image, inaccordance with another embodiment.

FIG. 3D shows an exemplary model of a quadrilateral digital image ofFIG. 3A that is located at the bottom-right corner of a digital image,in accordance with another embodiment.

FIG. 4A shows an exemplary electronic display panel system that is splitusing four regions or stripes.

FIG. 4B shows an exemplary electronic display panel system split usingwith four regions or quadrants.

FIG. 5 shows an exemplary way of scaling a digital image that is to bedisplayed using an electronic display panel that is split into fourregions.

FIG. 6A shows an exemplary digital image that is split into four regionswhere each region is to be scaled individually and then displayed usingan electronic display panel that is split into four regions, inaccordance with another embodiment.

FIG. 6B shows exemplary right margin and bottom margin pixels that areused for scaling the top-left region of the digital image of FIG. 6A, inaccordance with another embodiment.

FIG. 6C shows exemplary top margin and left margin pixels that are usedfor scaling the bottom-right region of the digital image of FIG. 6A, inaccordance with another embodiment.

FIG. 7A shows an exemplary partitioning of a digital image into multipleportions using M rows and N columns, in accordance with anotherembodiment.

FIG. 7B shows exemplary Top, Right, Bottom, and Left margin of threeexemplary portions, namely D(1,2), D(m,n) and D(M,N), of the digitalimage of FIG. 7A, in accordance with another embodiment.

FIG. 8A is a block diagram illustrating an exemplary system forprocessing a digital image in accordance with one embodiment.

FIG. 8B is a block diagram illustrating an exemplary input module forprocessing a digital image in accordance with one embodiment.

FIG. 8C is a block diagram illustrating an exemplary memory data pathcontroller for processing a digital image in accordance with oneembodiment.

FIG. 8D is a block diagram illustrating another exemplary input modulefor processing a digital image in accordance with one embodiment.

FIG. 8E is a block diagram illustrating an exemplary output displaymodule for processing a digital image in accordance with one embodiment.

FIG. 9A shows an exemplary digital image comprising six regions, each ofwhich is processed individually in accordance with one embodiment.

FIG. 9B shows an exemplary digital image comprising thirty-two lines andeach line comprises forty-eight pixels, in accordance with oneembodiment.

FIG. 9C shows an expanded view of the pixels of Region_(—)1, inaccordance with one embodiment.

FIG. 9D shows an exemplary memory organization of an exemplary digitalimage comprising thirty-two lines and each line comprises forty-eightpixels, in accordance with one embodiment.

FIG. 9E shows an exemplary quadrangle digital image comprisingRegion_(—)1, top, bottom, left, and right margin pixels, in accordancewith one embodiment.

FIG. 9F shows an exemplary quadrangle digital image, within the digitalimage of FIG. 9B, comprising Region_(—)1, and neighboring left andbottom pixels, in accordance with one embodiment.

FIG. 9G shows an expanded view of the exemplary quadrangle digital imageof FIG. 9F, in accordance with one embodiment.

FIG. 9H shows an expanded view of the exemplary quadrangle digital imageof FIG. 9G, and generated top margin and left margin pixels, inaccordance with one embodiment.

FIG. 9I shows an expanded view of the exemplary quadrangle digital imageof FIG. 9H, and generated right margin and bottom margin pixels, inaccordance with one embodiment.

FIG. 9J shows an exemplary quadrangle digital image, within the digitalimage of FIG. 9B, comprising Region_(—)2, and neighboring left, right,and bottom pixels, in accordance with one embodiment.

FIG. 9K shows an exemplary quadrangle digital image, within the digitalimage of FIG. 9A, in accordance with one embodiment.

FIG. 9L shows memory organization of the exemplary quadrangle digitalimage of FIG. 9K, within the memory organization of the exemplarydigital image of FIG. 9D, in accordance with one embodiment.

FIG. 9M shows an exemplary quadrangle digital image, within the digitalimage of FIG. 9A, in accordance with one embodiment.

FIG. 9N shows memory organization of the exemplary quadrangle digitalimage of FIG. 9M, within the memory organization of the exemplarydigital image of FIG. 9D, in accordance with one embodiment.

FIG. 9O shows an exemplary quadrangle digital image, within the digitalimage of FIG. 9A, in accordance with one embodiment.

FIG. 9P shows an exemplary quadrangle digital image, within the digitalimage of FIG. 9A, in accordance with one embodiment.

FIG. 10A shows an exemplary command structure for an exemplary memoryaccess request to write or read video data information to or from amemory device, in accordance with one embodiment.

FIG. 10B shows an alternate exemplary command structure for an exemplarymemory access request to write or read video data information to or froma memory device, in accordance with one embodiment.

DETAILED DESCRIPTION

The present disclosure provides, amongst other things, techniques tominimize or substantially eliminate artifacts when scaling lowresolution video or digital images to higher resolution digital imagesin order to be displayed using electronic display panels with two ormore defined regions. In one respect, a digital video comprises manysequential digital images that capture a certain scene for a certainperiod of time. A digital image is split into multiple regions and eachregion is then selectively processed and/or scaled so that it can bedisplayed using a correspondent region of the display. Each of themultiple regions is defined using a portion of the digital image and isspecified using a width and a height, in unit of pixel. In addition,neighboring pixels for each of the multiple regions are defined asmargins, e.g. Top margin, Right margin, Bottom margin, and Left marginthat will be described in details in this disclosure, and are specifiedto comprise pixels that are part of the digital image and/or newlygenerated pixels using various techniques such as on the fly or apredetermined data information. The combination of each of the multipleregions and all of its margins are then processed or scaled to produce aprocessed portion of the digital image. Furthermore, the concatenationof all of the processed portions of the digital image are thendisplayed, using electronic display panels with multiple definedregions, and thus faithfully reproduce the original digital image.

The disclosure and the various features and advantageous details areexplained more fully with reference to the nonlimiting embodiments thatare illustrated in the accompanying drawings and detailed in thefollowing description. Descriptions of well-known processing techniques,components, and equipment are omitted so as not to unnecessarily obscurethe invention in detail. It should be understood, however, that thedetailed description and the specific examples, while indicatingembodiments of the invention, are given by way of illustration only andnot by way of limitation. Various substitutions, modifications,additions, and/or rearrangements within the spirit and/or scope of theunderlying inventive concept will become apparent to those of ordinaryskill in the art from this disclosure. Other features and associatedadvantages will become apparent with reference to the following detaileddescription of specific embodiments in connection with the accompanyingdrawings.

The term “coupled” is defined as connected, although not necessarilydirectly, and not necessarily mechanically. The terms “a” and “an” aredefined as one or more unless this disclosure explicitly requiresotherwise. The terms “comprise” (and any form of comprise, such as“comprises” and “comprising”), “have” (and any form of have, such as“has” and “having”), “include” (and any form of include, such as“includes” and “including”) and “contain” (and any form of contain, suchas “contains” and “containing”) are open-ended linking verbs. As aresult, a method or device that “comprises,” “has,” “includes” or“contains” one or more steps or elements possesses those one or moresteps or elements, but is not limited to possessing only those one ormore elements. Likewise, a step of a method or an element of a devicethat “comprises,” “has,” “includes” or “contains” one or more featurespossesses those one or more features, but is not limited to possessingonly those one or more features. Furthermore, a device or structure thatis configured in a certain way is configured in at least that way, butmay also be configured in ways that are not listed.

In general, various processing techniques can be used to process orscale digital images from one specified resolution to another specifiedresolution. For example, newly available Quad-HD electronic displaypanels, or can be simply referred to as monitors, can display imagesusing a resolution of 3840×2160 pixels, or 3840 pixels in width and 2160pixels in height, for a total of 8,294,400 pixels. A high definitiondigital image may be specified using 1920 pixels in width and 1080pixels in height, or in other words a resolution of 1,920×1,080 for atotal of 2,073,600 pixels. As you can see The Quad-HD monitor is capableof displaying four times the number of pixels that define the digitalimage using four regions each of which is capable of displaying a full1,920×1,080 pixels. Normally a low resolution digital image is firstscaled to 3840×2160 resolution and then split into four regions, each ofwhich is then displayed using a corresponding region of the monitor. Thehigher the resolution of an available Quad-monitor is, the higher theprocessing requirement is to display a given digital image at the fullmonitor resolution. This disclosure describes a suitable solution tosolve the ever-increasing challenge of scaling a given digital image inorder to be faithfully reproduced and fully displayed using monitorswith multiple defined regions, e.g. Quad-HD monitor.

An exemplary model depicting a digital image 100 using pixels arrangedas a two-dimensional grid is shown in FIG. 1. The digital image 100 isdefined as having a Width 110 and a Height 120, in unit of pixel. Theresolution of Digital image 100 is therefore Width 110×Height 120pixels. Furthermore, the Digital image 100 is defined to have fouredges, namely, a Topmost edge 130, a Rightmost edge 140, a Bottommostedge 150, and a Leftmost edge 160. The Topmost edge 130 comprises everypixel on a straight line bounded by two end pixels, namely, theTop-leftmost pixel 135 and the Top-rightmost pixel 145. The Rightmostedge 140 comprises every pixel on a straight line bounded by two endpixels, namely, the Top-rightmost pixel 145 and the Bottom-rightmostpixel 155. The Bottommost edge 150 comprises every pixel on a straightline bounded by two end pixels, namely, the Bottom-rightmost pixel 155and the Bottom-leftmost pixel 165. The Leftmost edge 160 comprises everypixel on a straight line bounded by two end pixels, namely, theBottom-leftmost pixel 165 and the Top-leftmost pixel 135. The exemplarymodel of Digital image 100 will be used throughout the as a mean todescribe the underlying inventive concepts and should not be construedas a limitation of the disclosure. For example, the inventive conceptscan be applied to a digital image using pixels arranged in various waysincluding, for example, a three-dimensional grid.

Now referring to FIG. 2A, a region, D₁ 280, of the Digital image 200 isdefined as a quadrangle digital image that is surrounded by a Top edge232, a Right edge 242, a Bottom edge 252 and a Left edge 262. D₁ 280comprises all the pixels within the region including the pixels of theTop edge 232, the Right edge 242, the Bottom edge 252 and the Left edge262. Furthermore, D₁ 280 is specified to have a D₁ Width 212 and a D₁Height 222, in unit of pixel. An exemplary location of the region D₁ 280is shown in FIG. 2A to be within the Digital image 200, near its center.Various locations of the region D₁ 280 are possible within, andincluding, the boundary edges of the Digital image 200 as defined by aTopmost edge 230, a Rightmost edge 240, a Bottommost edge 250, and aLeftmost edge 260. For example, a possible location of D1 280 can be atthe top-leftmost corner of the Digital image 200 such that the Left edge262, of D₁ 280, is collinear with the Leftmost edge 260 of the Digitalimage 200. Furthermore, the Top edge 232, of D₁ 280, is collinear withthe Topmost edge 230 of the Digital image 200.

Referring to FIG. 2B, a Top margin 235 is defined as a certain number ofpixels in the vertical direction and above the Top edge 232, regardlessof whether the Top edge 232 is at the boundary of the Digital image 200,i.e. the Top edge 232 is collinear with the Topmost edge 230. Similarly,a Bottom margin 255 is defined as a certain number of pixels in thevertical direction and below the Bottom edge 252, regardless of whetherthe Bottom edge 252 is at the boundary of the Digital image 200, i.e.the Bottom edge 252 is collinear with the Bottommost edge 250. Inaddition, a Right margin 245 is defined as a certain number of pixels inthe horizontal direction and to the right of the Right edge 242,regardless of whether the Right edge 242 is at the boundary of theDigital image 200, i.e. the Right edge 242 is collinear with theRightmost edge 240. Similarly, a Left margin 265 is defined as a certainnumber of pixels in the horizontal direction and to the left of the Leftedge 262, regardless of whether the Left edge 262 is at the boundary ofthe Digital image 200, i.e. the Left edge 262 is collinear with theLeftmost edge 260. Subsequently, a new region of the Digital image 200can now be defined to comprise the region D₁ 280 and all of thesurrounding pixels as defined by the Top, Bottom, Right and Left marginsaround D₁ 280 regardless of whether any pixel of any one of the Top,Bottom, Right and Left margins exist within the Digital image 200. Thiswill be described in further details in the following paragraphs.

Referring to FIG. 3A, a newly defined quadrilateral digital image 305 isshown comprising a first region determined as quadrangle digital imageD₁ 380. The actual number of pixels, as drawn in FIG. 3A, will be usedas an additional illustrative mean in order to describe the relationshipbetween the quadrilateral digital image 305 and the quadrangle digitalimage D₁ 380. For example, D₁ 380 is determined using a D₁ Width 312,which corresponds to seven pixels as shown, and a D₁ Height 322, whichcorresponds to four pixels as shown. Thus, the resolution of the regiondefined by D₁ 380 is determined to be 7×4, or a total of 28 pixels.Furthermore, the four edges of the quadrangle digital image D₁ 380 aredefined as follows: a Top edge 332 comprising the seven topmost pixelsof D₁ 380, a Right edge 342 comprising the four rightmost pixels of D₁380, a Bottom edge 352 comprising the seven bottommost pixels of D₁ 380,and a Left edge 362 comprising the four leftmost pixels of D₁ 380. It isthus clear that the region D₁ 380 comprises all the pixels that aredetermined to be within its four edges including the pixels located atthe Top edge 332, the Right edge 342, the Bottom edge 352 and the Leftedge 362. We will now describe a second region of the quadrilateraldigital image 305.

In one embodiment, the second region of the quadrilateral digital image305 is determined using a Top margin 335, a Right margin 345, a Bottommargin 355, and a Left margin 365 using the same number of pixels. Forexample, each of the Top margin 335, the Right margin 345, the Bottommargin 355, and the Left margin 365 comprises at least one pixel. Anexemplary margin of two pixels is used for all Top, Right, Bottom, andLeft margins, as shown in FIG. 3A. The quadrilateral digital image 305is then determined and is specified using a Q₁ Width 314 and a Q₁ Height324, in accordance with the following relationships:

Q ₁ Width 314=(Left Margin 365+D ₁ Width 312+Right Margin 345)  Eq. 1

Q ₁ Height 324=(Top Margin 335+D ₁ Height 322+Bottom Margin 355)  Eq. 2

Accordingly, for the exemplary drawing shown in FIG. 3A, the Q₁ Width314 is computed to be eleven pixels, (2+7+2), and the Q₁ Height 324 iscomputed to be eight pixels, (2+4+2). Therefore, the total resolution ofthe quadrilateral digital image 305 is 11×8 or a total of 88 pixels ascompared with a 7×4 or a total of 28 pixels for D₁ 380. Furthermore, thequadrangle digital image D₁ 380 is centered within the quadrilateraldigital image 305 using the Top margin 335, the Right margin 345, theBottom margin 355, and the Left margin 365. In another embodiment, eachof the Top margin 335, the Right margin 345, the Bottom margin 355, andthe Left margin 365 may be defined using a different number of pixels,and therefore the quadrangle digital image D₁ 380 may somewhat beoff-centered within the quadrilateral digital image 305 as would bedetermined by the number of margin pixels.

In accordance with one embodiment, the data information for each pixellocated in any of the Top margin 335, the Right margin 345, the Bottommargin 355, and the Left margin 365 is generated using existing datainformation from any one pixel of the quadrangle digital image D₁ 380,or using predetermined color data information, or any combinationthereof. The predetermined color data information may corresponds to anycolor including black color. In accordance with another embodiment, aTop Wing 337 is defined to comprise at least one row of pixels that arelocated directly above the Top Edge 332. For example, the Top Wing 337comprises two pixels, identified as Top Wing e-pixel 338, that areimmediately above the correspondent pixel, Top Edge e-pixel 333, in thevertical direction, as shown in FIG. 3A. In accordance with yet anotherembodiment, the Top Wing 337 is defined to comprise at least one pixel,Top Wing e-pixel 338, that is directly above a correspondent pixel, TopEdge e-pixel 333, in the vertical direction. It is important to notethat the Top Wing e-pixel 338 data information may be generated usingvarious direct or indirect manipulation, duplication, or management ofthe data information of the pixel, Top Edge e-pixel 333, as is generallyknown to those of ordinary skill in the art. In accordance with anotherembodiment, the Top Wing e-pixel 338 data information is generated usingthe data information of the pixel, Top Edge e-pixel 333, or any otherpixel that is located on the Top edge 332. In accordance with yetanother embodiment, the Top Wing e-pixel 338 data information isgenerated using direct or indirect manipulation, duplication, ormanagement of the data information of the pixel, Top Edge e-pixel 333,in combination with a predetermined data information that maycorresponds to specific color, for example black, gray or any othercolor. In accordance with a preferred embodiment, the Top Wing e-pixel338 data information is generated, on the fly during the processing ofthe quadrangle digital image D₁ 380, using data information of thepixel, Top Edge e-pixel 333, or any other pixel that is located on theTop edge 332. In accordance with yet another preferred embodiment, theTop Wing e-pixel 338 data information is generated, on the fly duringthe processing of the quadrangle digital image D₁ 380, using any one, ora combination, of the embodiments described above. In addition, a BottomWing 357 comprises at least one row of pixels that are located directlybelow the Bottom Edge 352. The data information for the Bottom Wing 357pixels is generated, using corresponding pixels that are located on theBottom Edge 352 and in a similar fashion and means as described abovefor the Top Wing 337.

In accordance with a preferred embodiment, a Left Wing 367 comprises atleast one column of pixels that is located immediately to the left ofthe Left Edge 362 of the quadrangle digital image D₁ 380. The datainformation for the Left Wing 367 pixels is generated using datainformation of the corresponding pixels that are identified as theleftmost pixels of the Top Wing 337, Top Wing e-pixel 338 as shown thein FIG. 3A, the pixels of the Left Edge 362 of the quadrangle digitalimage D₁ 380, and the leftmost pixels of the Bottom Wing 357, and in asimilar fashion and means as described above for the Top Wing 337. Forexample, the data information for the Left Wing 367 pixels can begenerated using a direct or indirect manipulation, duplication, and/ormanagement processes of the data information of the pixels that arelocated on any one of the edges of the quadrangle digital image D₁ 380.Furthermore, the data information can be created using predeterminedcolor information, including data information that corresponds to blackcolor, or any other color. Any combination of the above methods may beemployed singularly or in combination to generate the data informationfor the Left Wing 367 pixels thereof. In addition, various methods basedon mathematical or algorithmic means to generate, possibly on the fly,the data information needed for each of the margin pixels may also beused and may be implemented in combination of any of the other methodsdescribed above. Similarly, a Right Wing 347 comprises at least onecolumn of pixels that is located immediately to the right of the RightEdge 342 of the quadrangle digital image D₁ 380. The data informationfor the Right Wing 347 pixels is generated using data information of thecorresponding pixels that are identified as the rightmost pixels of theTop Wing 337, the pixels of the Right Edge 342 of the quadrangle digitalimage D₁ 380, and the rightmost pixels of the Bottom Wing 357, and in asimilar fashion and means as described above for the Top Wing 337,including various methods as described above.

In another embodiment, changing the order of the data information thatis generated first, i.e. Right Wing 347 & the Left Wing 367, and thendata information for the Top Wing 337 & the Bottom Wing 357 would resultin a change of the number of pixels being processed in each of the stepsidentified above for each one of the Right Wing 347, the Left Wing 367,the Top Wing 337, and the Bottom Wing 357 but does not change theunderlying inventive concepts as described above and this flexibilitywould be appreciated by those skilled in the art. As will be describedand shown in the following paragraphs, the definition of thequadrilateral digital image 305 will be used in the processing of anarbitrary digital image, which is split into multiple quadrangleregions, D₁, D₂, D₃, . . . , D_(z). The margin pixels are then eitherdetermined or created, as described above, for each of the multiplequadrangle regions, D_(z). Sometimes these margin pixels are part of thearbitrary digital image and sometimes the margin pixels are generatedbased on any one, or any combination, of methods as described above. Anew quadrilateral digital image, Q_(z), is then created from theconcatenation of each of the multiple quadrangle regions, D_(z), and itsown margin pixels.

Now referring to FIG. 3B, an exemplary digital image 300 comprising aquadrilateral digital image 305 and a quadrangle digital image 380, asdescribed in the above. A D₁ Width 312 and D₁ Height 322 define thequadrangle digital image 380. Accordingly, Q₁ Width 314 and Q₁ Height324 define the quadrilateral digital image 305 and are determined inaccordance with Eq. 1 and Eq. 2 listed above. In accordance with oneembodiment, the quadrilateral digital image 305 is within any one of aTopmost edge 330, a Rightmost edge 340, a Bottommost edge 350, and aLeftmost edge 360 of the digital image 300, as shown in FIG. 3B. Inaccordance with another embodiment, the quadrilateral digital image 305is located at the top-left corner of the digital image 300, as shown inFIG. 3C. In accordance with yet another embodiment, the quadrilateraldigital image 305 is located at the bottom-right corner of the digitalimage 300, as shown in FIG. 3D. Therefore, the location of thequadrangle digital image 380 within the digital image and the depth ofeach of the Top margin 335, the Right margin 345, the Bottom margin 355,and the Left margin 365 will determine the location of the margin pixelsand thus the pixels' data information is determined using variousmethods as described above. In accordance with one embodiment, if themargin pixels are located within anyone of the Topmost edge 330, theRightmost edge 340, the Bottommost edge 350, and the Leftmost edge 360of the digital image 300 then the data information is duplicated fromthe correspondent pixels of digital image 300. In accordance withanother embodiment, if the margin pixels are located beyond anyone ofthe Topmost edge 330, the Rightmost edge 340, the Bottommost edge 350,and the Leftmost edge 360 of the digital image 300 then the datainformation is generated or created using various methods as describedabove. Please note that an effort is made to keep the nomenclature ofFIG. 3A through FIG. 3D consistent, with the exception of the locationof the quadrilateral digital image 305 within the digital image 300, seeFIG. 3B through FIG. 3D. Some objects names were left off some of FIG.3A-D for increasing the drawing clarity, it is clear that FIG. 3Athrough FIG. 3D are used to show exemplary locations of quadrilateraldigital image 305 for illustrative purposes.

Therefore, data information is generated for certain margin pixels thatare determined to be beyond the Topmost edge 330 and the Leftmost edge360, see FIG. 3C. The remaining margin pixels that are determined to bewithin the Rightmost edge 340 and the Bottommost edge 350, wouldcomprise data information from the correspondent pixels of the digitalimage 300. In accordance with one embodiment, data information isgenerated for at least one pixel of the quadrilateral digital image 305that is above the Topmost edge 330 of the digital image 300 if the Topedge 332 of the quadrangle digital image 380 is collinear with theTopmost edge 330 of the digital image 300. Similarly, data informationis generated for at least one pixel of the quadrilateral digital image305 that is to the left of the Leftmost edge 360 of the digital image300 if the Left edge 362 of the quadrangle digital image 380 iscollinear with the Leftmost edge 360 of the digital image 300. Variousmethods and steps may be used, as described above. However, the datainformation for each margin pixel may be generated based on at least oneof the following: (i) using data information of at least one pixel thatis located on the Top edge 332 of the quadrangle digital image 380, (ii)using data information of at least one pixel that is located to the leftof the Top edge 332 of the quadrangle digital image 380 (see FIG. 3B),(iii) using data information of at least one pixel that is located tothe right of the Top edge 332 of the quadrangle digital image 380, (iv)using data information of at least one pixel that is located anywhere onthe Topmost edge 330 of the digital image 300, and (v) using datainformation that corresponds to any color, including black.

Now referring to FIG. 3D, data information is generated for certainmargin pixels that are determined to be beyond the Bottommost edge 350and the Rightmost edge 340. The remaining margin pixels that aredetermined to be within the Leftmost edge 360 and the Topmost edge 330,would comprise data information from the correspondent pixels of thedigital image 300. In accordance with one embodiment, data informationis generated for at least one pixel of the quadrilateral digital image305 that is below the Bottommost edge 350 of the digital image 300 ifthe Bottom edge 352 of the quadrangle digital image 380 is collinearwith the Bottommost edge 350 of the digital image 300. Similarly, datainformation is generated for at least one pixel of the quadrilateraldigital image 305 that is to the right of the Rightmost edge 340 of thedigital image 300 if the Right edge 342 of the quadrangle digital image380 is collinear with the Rightmost edge 340 of the digital image 300.Various methods and steps may be used, as has been described above.However, the data information for each margin pixel may be generatedbased on at least one of the following: (i) using data information of atleast one pixel that is located on the Bottom edge 352 of the quadrangledigital image 380, (ii) using data information of at least one pixelthat is located to the left of the Bottom edge 352 of the quadrangledigital image 380, (iii) using data information of at least one pixelthat is located to the right of the Bottom edge 352 of the quadrangledigital image 380 (see FIG. 3B), (iv) using data information of at leastone pixel that is located anywhere on the Bottommost edge 350 of thedigital image 300, and (v) using data information that corresponds toany color, including black.

An electronic display panel, may be referred to as monitor, are used inan ever increasing number of applications that generates very highresolution digital images or demands the ability to display multiplehigh resolution images. One such exemplary monitor is shown in FIG. 4A,where the monitor device 400 screen (or panel) is split into fourStripes, namely Stripe 410, Stripe 420, Stripe 430, and Stripe 440 thatcorresponds to the actual screen region define by the panel Region 0,Region 1, Region 2, and Region 3 respectively. Every one of Region 0,Region 1, Region 2, and Region 3 corresponds to a high definition, HD,picture resolution, namely 1920×1080. The splitting of the monitordevice 400 screen into four HD regions would overcome many of thechallenges associated with the production of a monitor with a singleregion having a resolution of 3840×2160, and would be at a lower costand more power efficient. Such monitors are currently available and maybe referred to as Quad-HD monitor. The splitting of the screen intomultiple regions does present several challenges. For example, whenusing an HD resolution digital image, it can be displayed well withinany one of the four regions of the monitor device 400, namely Region 0,Region 1, Region 2, and Region 3. However, the resultant displayed imagewill suffer from artifacts at the boundaries of the four regions wherethe resultant pixels of each region may not be properly or timely placedor aligned with the pixels of the adjacent region.

An exemplary process of displaying an Image 510 using a Scaled image 515and a quad display Monitor 595 will be described as shown FIG. 5. First,the Image 510 is scaled up to a resolution that correspond to theresolution of the Monitor 595. The Scaled image 515 is split into fourquadrangle scaled images, namely Scaled image 520, Scaled image 530,Scaled image 540, and Scaled image 550. Each of the four quadranglescaled images having a resolution that correspond to the resolution of acorrespondent region of Monitor 595, namely Monitor 560, Monitor 570,Monitor 580, Monitor 590, such that Quad 0 of the Scaled image 520 isdisplayed using the display region defined by Quad 0 of Monitor 560.Other quadrants of the Scaled image 515 are then respectively displayedusing the appropriate quadrant of the display Monitor 595. Accordinglythe consequential display of the individual four quadrant of Monitor 595should reproduce the original Image 510 using the full resolution ofMonitor 595. However, annoying visual artifacts resulting from theimproper alignment of the displayed pixels located at a common verticalMonitor boundary 562 and/or a horizontal Monitor boundary 564 can beeasily viewed especially during video playback of fast moving objectsacross the four quadrants of the display Monitor 595. The inventiveconcepts developed by Marseille Networks and described above will beused and described in the following paragraph to faithfully reproducethe Image 510 using Monitor 595 with multiple defined regions.

Referring to FIG. 6A, the process of displaying an Image 610 usingMonitor 695 having four quadrant, namely Monitor 660, Monitor 670,Monitor 680, Monitor 690 is described in accordance with one embodiment.An Image 611 is a processed version of Image 610. The Image 611 is splitinto four regions, namely Split image 620, Split image 630, Split image640, and Split image 650, that corresponds to and in proportion to thenumber of regions of the Monitor 695, namely Monitor 660, Monitor 670,Monitor 680, Monitor 690 respectively. Each one of the Split image 620,Split image 630, Split image 640, and Split image 650 is individuallyprocessed and scaled up to the resolution required by the correspondentregion of the Monitor 695. In another embodiment, if the Image 610 isalready at the full resolution of Monitor 695, then there may not be aneed for any processing to produce Image 611, and the Image 611 may besame as Image 610. The processing of each of the Split image 620, Splitimage 630, Split image 640, and Split image 650 may not include scalingsince each of the individual regions of the Image 611 is already at thefull resolution of the correspondent region of the Monitor 695.

Now referring to FIG. 6B, and using a Split Image 620, corresponding toQuad 0, as an exemplary region of the Image 611 for processing.Exemplary pixels, for illustrative purposes, are arranged intwo-dimensional grid format over the entire region, Quad 0, and aTop-leftmost pixel 621 is shown at the top left corner of the Splitimage 620. The inventive concepts described above are applied to theSplit image 620, which corresponds to a quadrangle digital image to beprocessed. Since the region, Quad 0, is at the top-left quadrant of theImage 611, then a Right margin 624 and a Bottom margin 625 are generatedfrom existing pixels that are part of Split image 630, Split image 640,and Split image 650, as shown in FIG. 6B. Furthermore, since the region,Quad 0, is at the top-left quadrant of the Image 611, then top edge ofSplit image 620 is collinear with the topmost edge of the Image 611.Similarly, the left edge of Split image 620 is collinear with theleftmost edge of the Image 611. Therefore, a Top margin 623 and a Leftmargin 626 are created using any one, or a combination of variousmethods as described above. In order to keep the clarity of the drawingsas shown in FIG. 6A through 6C some objects have not been named but theintended meaning should be very clear from FIGS. 6A-6C and whilereferencing back to the detailed drawings of FIG. 3A through FIG. 3D.

A Digital image 710 having a topmost edge, a bottommost edge, a leftmostedge, and a rightmost edge is split into M rows and N columns, and thusdefining an M×N array of quadrangle digital images, each of which isidentified as D_((m,n)), as shown in FIG. 7A. The index m represent anyone integer of a first range of consecutive integers, wherein the firstrange corresponds to the number of rows M, and a column index, n, thatis any one integer of a second range of consecutive integers, whereinthe second range corresponds to the number of columns N. In accordancewith one embodiment, every element of the M×N array correspond to aregion comprising a quadrangle digital image, and the inventive conceptsas described above are applied to each region individually. Inaccordance with another embodiment, multiple of the elements of the M×Narray may be combined to form a single quadrangle digital image and thuscan be processed accordingly.

Margin pixels are determined for an exemplary D_((1,2)), D_((m,n)) andD_((M,N)) as shown in FIG. 7B, for illustrative purposes. A Top margin751, a Bottom margin 753, a Left margin 754, and a Right margin 752. Anew quadrilateral digital images, Q_((m,n)), is generated comprising theD_((m,n)) portion of the digital image, as defined by the array elementthat corresponds to the quadrangle digital image D_((m,n)), and a secondportion of the digital image, defined by the Top margin 751, the Bottommargin 753, the Left margin 754, and the Right margin 752. Each newquadrilateral digital images Q_((m,n)) is larger than the correspondingD_((m,n)) and in accordance with the following relationships:

Q _((m,n))width=Left margin+D _((m,n))width+Right margin,  Eq. 3

Q _((m,n))height=Top margin+D _((m,n))height+Bottom margin,  Eq. 4

Each of the quadrangle digital images D_((m,n)) is centered within thequadrilateral digital image Q_((m,n)) using the Top margin 751, theBottom margin 753, the Left margin 754, and the Right margin 752. Inaddition, at least a first pixel of the quadrilateral digital imageQ_((m,n)) is determined to be located beyond any one of the topmostedge, the bottommost edge, the leftmost edge, and the rightmost edge ofthe Digital image 700 if any one of a D_((m,n)) top edge, a D_((m,n))bottom edge, a D_((m,n)) left edge, and a D_((m,n)) right edge of aquadrangle digital image D_((m,n)), is collinear with any one of thetopmost edge, the bottommost edge, the leftmost edge, and the rightmostedge of the Digital image 700. Appropriate data information is generatedfor the first pixel based on at least one of the following steps: (i)using data information of at least one pixel that is located on any oneof the D_((m,n)) top edge, the D_((m,n)) bottom edge, the D_((m,n)) leftedge, and the D_((m,n)) right edge of the correspondent quadrangledigital image D_((m,n)), (ii) using data information of at least onepixel that is located on any one of the topmost edge, the bottommostedge, the leftmost edge, and the rightmost edge of the Digital image700, and (iii) using data information that corresponds to any color,including black.

In a similar fashion, data information for all margin pixels isdetermined first by checking if the margin pixels are within the Digitalimage 700 or are beyond any one of the topmost edge, the bottommostedge, the leftmost edge, and the rightmost edge of the Digital image700. Various method of generating and/or creating data information formargin pixels have been described in details in this disclosure and usedhere for every quadrilateral digital image Q_((m,n)). In accordance withanother embodiment, it should be noted that the general solutiondescribed above for splitting any Digital image 700 into an array of M×Narray of quadrangle digital images is not limited to two-dimensionalarrangement of all elements of the array. For example, multi-dimensionalarrangement of (M×N×Z) array of quadrangle digital images would benefitgreatly and the inventive concepts here are easily applied to eachelement of the multi-dimensional arrangement of array that correspondsto a quadrangle digital image.

A block diagram of a Digital Image Processing System 800 is shown inFIG. 8A and is briefly described. Digital images can be formed,transmitted, stored, or displayed using a video format standard thatspecifies how video data information for each pixel is generated.Currently, many video format standards are used around the world.Various types of image capturing systems can capture video datainformation of digital images in accordance with at least one videoformat standard, and is able to transfer the video data information ofthe digital images by using corresponding signals over a wired orwireless connection. The Digital Input Data Path 811 comprises multipleconductors to transfer video data information signals of a digital imageto an Input Module 810. An example of a digital image comprising twohundred forty pixels organized in twelve lines and each line comprisingtwenty pixels is shown in FIG. 1 as Digital Image 100. The Input Module810 captures and processes the video data information of the digitalimage, and initiates memory write transaction to store the processedvideo data information of the digital image into a Memory 850 using aMemory Data Path Controller 830 via a First Memory Data Path 831 and aSecond Memory Data Path 832. A Register and Control Module 820 comprisesprogrammable registers to store operational data information for theprocessing of the captured video data information of the digital imagethroughout the Digital Image Processing System 800. The Register andControl Module 820 further comprises logic circuitry needed to respondto and communicate with various modules and components of the DigitalImage Processing System 800 via a First Control Data Path 821. Inaddition, the Register and Control Module 820 is coupled to a SecondControl Data Path 822 providing a user interface to gain access to,communicate with, respond to, and control various functions of theDigital Image Processing System 800. The Memory Data Path Controller 830communicates with the Input Module 810 and an Output Module 840 via theFirst Memory Data Path 831. The Memory Data Path Controller 830communicates exclusively with the Memory 850 via the Second Memory DataPath 832. Furthermore, the Memory Data Path Controller 830 is coupled tothe Register and Control Module 820 via the First Control Data Path 821.The Output Module 840 retrieves video data information from the Memory850 using the Memory Data Path Controller 830 and via the First andSecond Memory Data Path, 831 and 832 respectively. Furthermore, theOutput Module 840 processes the retrieved video data information, andoutputs a processed version of the digital image onto the Output DisplayData Path 846. The Output Module 840 is capable of driving highdefinition electronic display systems comprising multiple regions, whereeach region displays a portion of the overall digital image to bedisplayed. The Output Module 840 comprises output display modulesODM_(—)1, ODM_(—)2, ODM_(—)3, ODM_(—)4, through ODM_k, where “k”corresponds to the total number of regions and is equivalent to “m” rowsmultiplied by “n” columns, relative to how the electronic display isdivided into “m” rows and “n” columns, e.g. as shown in FIG. 7B.Detailed description of various parts, components, modules and theoperation of the Digital Image Processing System 800 will be provided inthe following paragraphs.

The Memory Data Path Controller 830 handles as many memory accessrequests as needed for all the output display modules ODM_(—)1 throughODM_k, which are part of the Output Module 840, so that the video datainformation of the Digital Image 900 is processed as desired. The accessefficiency to and from Memory 850 has a large impact on the scalabilityof the Digital Image Processing System 800, and the overall video datainformation processing throughput. Various modes or types of memoryaccess are used and the Memory Data Path Controller 830 provides theability to handle different types of back-to-back memory accessrequests. The design and performance of the Second Memory Data Path 832and the First Memory Data Path 831 contribute as well to the overallperformance and efficiency desired. The component, modules andfunctional description of the Digital Image Processing System 800, asshown in FIG. 8A, is meant as an exemplary guide of how video datainformation of a digital image is captured from a Digital Input DataPath 811, processed, and outputted to multiple regions of an electronicdisplay system using the Output Display Data Path 846. Various alternateembodiments are discussed in various levels of details in the followingparagraphs as to further show the flexibility of the Digital ImageProcessing System 800 architecture and should not be considered as alimitation of the embodiments. It is important to note that the DigitalImage Processing System 800 comprises many other blocks, sub-systems,control signals, Clock modules, signal interface circuitry, PLL etc. . .. , which are not shown in FIG. 8A in order to maintain clear drawings.

The Input Module 810 comprises three main components, an Input Capture810_(—)10 coupled to the Digital Input Data Path 811 and a VideoFormatter 810_(—)20, and a Memory Interface 810_(—)30 coupled to theFirst Memory Data Path 831 and the Video Formatter 810_(—)20, as shownin the block diagram of FIG. 8B. The Input Capture 810_(—)10 compriseslogic circuitry to receive video data information, of an input digitalimage, via the Digital Input Data Path 811, in accordance with a videoformat standard. Depending on the design requirement, the Digital ImageProcessing System 800 may accommodate many different video formats. Anexemplary video format of the video data information of the inputdigital image is shown below:

1. RGB 4:4:4, 24 bits per pixel2. YUV 4:4:4, 24 bits per pixel3. YUV 4:2:2, 16 bits per sample, YU, YV, YU etc.4. YUV 4:2:2, 8 bits per sample, U, Y, V, Y, U etc.In addition, the video format standard specifies display controlinformation such as Vertical and Horizontal synchronization, Vsync andHsync, information that corresponds to and provides informationregarding how the pixels of the input digital image are arranged inaccordance with the resolution and the video format standard of theinput digital image. A pixel data enable signal, which may be triggeredfrom the Vsync signal, may be added to indicate the presence of validlines (or rows) of pixels to be captured or displayed. Alternatively, apixel data enable signal, which may be triggered from the Hsync signal,may be used to indicate the presence of valid pixels, within a line (orrows) of pixels, to be captured or displayed. Thus, the ability tocontrol the blanking, or the display, of a portion of the input digitalimage is enhanced by using appropriate data enable signals. Furthermore,the Digital Input Data Path 811 comprises at least one channel totransfer video data information signals to be received by the InputCapture 810_(—)10 from a digital image source. The channel may compriseone or multiple conductors to carry the video data information signal inaccordance with various desired signaling schemes, e.g. Low VoltageDifferential Signaling or LVDS. In certain application, some digitalimage sources may require multiple channels to carry the video datainformation of the digital image; this is especially true whenever thedigital image resolution is large enough such that the available channelbandwidth is not large enough to enable the transfer of the requiredvideo data information. In a preferred embodiment, the Digital InputData Path 811 comprises four input channels, where each channelcomprises five differential pairs of conductor and can operate at avariable frequency rate in accordance with the video format standard ofthe input video data information stream, e.g. 24-bit RGB 4:4:4 operatingat a frequency of 74.25 MHz. In accordance with another embodiment, theoutput of multiple digital image sources may be coupled to the DigitalInput Data Path 811, where at least one channel may be used to transfertheir video data information to one or multiple instances of the InputCapture 810_(—)10 module, as will be described and discussed later on inthis disclosure.

The Input Module 810 further comprises logic circuitry to receive orgenerate a first clock that is associated with the video datainformation. The Input Capture 810_(—)10, Video Formatter 810_(—)20 andMemory Interface 810_(—)30 may use this first clock for their operation.Multiples clocks may be generated from, or in addition to, the firstclock as may be required. For example, the first clock may be inputtedto a Phase Locked-Loop (PLL) or other types of circuitry to maintain anddistribute clocks to other components of the Digital Image ProcessingSystem 800. An output video display clock may also be derived from orlinked to the first clock, thus providing the ability for the outputdisplay to be locked to the input video data information stream. As ithas been mentioned earlier, various blocks or components may not beshown or discussed since their details is not necessary for a person ofordinary skills in the art to understand and practice the invention.Furthermore, the Digital Image Processing System 800 may comprise acentral processing unit CPU and its associated components, e.g.software, firmware and hardware, where some of the Digital ImageProcessing System 800 operations may be executed, managed, defined,substituted for one or more modules, configured or programmed to producethe desired system functions.

In accordance with one embodiment, the Video Formatter 810_(—)20receives a first digital image that is captured by the Input Capture810_(—)10 using a first video format, e.g. RGB 4:4:4, having twenty-fourbits for every pixel of the digital image. The Video Formatter 810_(—)20generates at least a second and third digital image, based on a secondvideo format e.g. YUV 4:2:2, using the first digital image received. Thesecond digital image comprises the luminance video data information (Y)of the digital image, while the third digital image comprises thechrominance video data information (UV) of the first digital image. TheMemory Interface 810_(—)30 generates at least one first memory writecommand to transfer the video data information of the second digitalimage to the Memory Data Path Controller 830 via the First Memory DataPath 831. The total number of memory write command required to transferthe video data information of the second digital image depends on thearchitecture of Digital Image Processing System 800. Various techniquesmay be used where one or multiple memory write commands may be used toeffect the complete transfer of the video data information from theInput Module 810 to the Memory 850. An exemplary transfer of video datainformation to the Memory 850 is described in the following paragraphs.

The Memory Data Path Controller 830 receives the first memory writecommand via the First Memory Data Path 831 and generates at least onefirst memory device write command to effect a transfer of the video datainformation of the second digital image to the Memory 850 via the SecondMemory Data Path 832. The first memory write command comprises a firstbase index that is used by the Memory Data Path Controller 830 togenerate a first base address that indicates a starting address of afirst region within the Memory 850, where the video data information ofthe second digital image is to be stored. The Memory Data PathController 830 embeds the first base address within the first memorydevice write command. Furthermore, the Memory 850 comprises controlcircuitry to receive the first memory device write command, and furthercomprises receive circuitry to receive the second video data informationvia the Second Memory Data Path 832. The Memory 850 writes the secondvideo data information into the first region of the Memory 850 startingfrom the memory location as indicated by the first base address.Additional data information, which may be embedded in the memory devicewrite or read commands, may be used to further specify an offset addressfor the starting memory location or how many memory locations are to beused for storing the video data information, as will be described theparagraphs below.

The Memory Interface 810_(—)30 generates at least one second memorywrite command to transfer the video data information of the thirddigital image to the Memory Data Path Controller 830 via the FirstMemory Data Path 831. The Memory Data Path Controller 830 receives thesecond memory write command via the First Memory Data Path 831 andgenerates at least one second memory device write command to effect atransfer of the video data information of the third digital image to theMemory 850 via the Second Memory Data Path 832. The second memory writecommand comprises a second base index that is used by the Memory DataPath Controller 830 to generate a second base address that indicates astarting address of a second region within the Memory 850, where thevideo data information of the third digital image is to be stored. TheMemory Data Path Controller 830 embeds the second base address withinthe second memory device write command. Furthermore, the Memory 850comprises control circuitry to receive the second memory device writecommand, and further comprises receive circuitry to receive the thirdvideo data information via the Second Memory Data Path 832. The Memory850 writes the third video data information into the second region ofthe Memory 850 starting from the memory location as indicated by thesecond base address.

Now referring to FIG. 8C, the Memory Data Path Controller 830 comprisesa First Memory Interface 830_(—)10 to receive the second video datainformation from the First Memory Data Path 831, in response to at leastone first memory write command. The Memory Data Path Controller 830further comprises Control 830_(—)20 logic circuitry to manage, aggregateand/or control the video data information flow and generate thenecessary information to initiate a memory device write transactionusing the information embedded in the memory write command. The Control830_(—)20 manages and provides the appropriate buffering for at least aportion of the second video data information being received whilewaiting to complete the memory device write transaction. The SecondMemory Interface 830_(—)30 generates at least one first memory devicewrite command, using the information extracted or generated in responseto the memory write command, and starts to send the received secondvideo data information to the Memory 850 via the Second Memory Data Path832. The second video data information is stored in the first region ofMemory 850 using the embedded first base address of the starting memorylocation, as described above. The third video data information istransferred in a similar fashion from the Input Module 810 to the secondregion of the Memory 850, in response to at least one second memorywrite command and at least one second memory device write command.Furthermore, the Memory Data Path Controller 830 provides management andcontrol of data information flow to and from the Memory 850 via theSecond Memory Data Path 832 in response to other modules requests formemory access. For example, the Memory Data Path Controller 830 providesmanagement and control of data information flow to and from the InputModule 810 and Output Module 840, via the First Memory Data Path 831,such that the Digital Image Processing System 800 is able to handlemultiple, back-to-back, or simultaneous memory access requests to andfrom Memory 850. Furthermore, the Memory Data Path Controller 830 hasthe mechanisms to handle synchronous and asynchronous conditions, andhas the capability to interface and control data information flow to andfrom various components of the Digital Image Processing System 800 asmay be necessary, where each component may be using different clockdomains.

The Register and Control Module 820 provides the necessary access andoperational settings to various programmable components, e.g. registers,within the Digital Image Processing System 800 via the First ControlData Path 821. In addition, the Second Control Data Path 822 providesthe necessary interface, e.g. I²C, for an external device to access andset various programmable registers of various components and modules ofthe Digital Image Processing System 800 via the First Control Data Path821. The Register and Control Module 820 performs all bus protocols toread and write internal registers, with both round-robin arbitration anda full acknowledge handshake to enable cross-clock-domain operation.Furthermore, the Digital Image Processing System 800 may comprise a ReadOnly Memory (ROM) that contains the default configuration that theRegister and Control Module 820 uses to program various modules onpower-up. Hence, relieving an external device from using the SecondControl Data Path 822 to program the Digital Image Processing System 800registers to a default power-up state. The Register and Control Module820 can service multiple clients within the Digital Image ProcessingSystem 800 via the First Control Data Path 821 and at least one externalclient via the Second Control Data Path 822. In the followingparagraphs, an exemplary write and read transactions through theRegister and Control Module 820 are briefly described.

A source module set a request for a write command for a specificregister of a specific module. The address of the specific register andthe address of the specific module are embedded within the writecommand. The source module can be any one of the Digital ImageProcessing System 800 internal modules, where the write command is sentvia the First Control Data Path 821, or an external module, where thewrite command is sent via the Second Control Data Path 822. Thedestination module can be any one of the Digital Image Processing System800 internal modules. The Register and Control Module 820 detects thewrite command and in turn places the write address for that request on aregister address bus portion of the First Control Data Path 821, andplaces the write data on a register write data bus portion of the FirstControl Data Path 821. The Register and Control Module 820 thenactivates the decoded write strobe for the destination module. Clocksynchronization may be implemented to insure the destination module willreceive proper write strobe, e.g. dual-rank synchronization of the writestrobe. In response to the write strobe, the destination module samplesthe data, registers address, and writes the data to the appropriateinternal register location within the destination module as indicated bythe register address. At that time, the destination module may send anacknowledge signal to the Register and Control Module 820. Thedestination module may hold the acknowledge signal true until it detectsthe release of the write strobe from the Register and Control Module820. The Register and Control Module 820 may further dual-ranksynchronizes the returning acknowledge signal before using it to decideto release the write strobe. Once the write strobe is released, theRegister and Control Module 820 is able to perform another read or writetransaction. In an alternate embodiment, the write strobe may be used todesignate a write cycle to multiple registers at the same time. Thewrite command specifies a broadcast type of command indicating a rangeof registers to be written at the same time with the same data. In yetanother embodiment, the write strobe may be used to designate a writecycle to multiple registers that are located in different modules at thesame time. The write command specifies a broadcast type of commandindicating the address of one or multiple registers to be written. Allthe destination modules that receives the broadcast type write command,initiate a write cycle to their register as identified by the registeraddress within the command cycle. This can produce an efficient and fastway to reconfigure Digital Image Processing System 800, e.g. when imagesize changes or when a change in video format standard is detected orrequired. An exemplary register read request is described in the nextparagraph.

A source module set a request for a read command of a specific registerwithin a specific module. The address of the specific register and theaddress of the specific module are embedded within the read command. Thesource module can be any one of the Digital Image Processing System 800internal modules, where the read command is sent via the First ControlData Path 821, or an external module, where the read command is sent viathe Second Control Data Path 822. The destination module can be any oneof the Digital Image Processing System 800 internal modules. TheRegister and Control Module 820 detects the read command and in turnplaces the read address for that request on the register address busportion of the First Control Data Path 821. The Register and ControlModule 820 then activates the decoded read strobe for the destinationmodule. Read strobe synchronization is achieved in a similar fashion tothe write strobe synchronization, as described above, e.g. dual-ranksynchronization of the read strobe. The destination module places theread data on a read data bus portion of the First Control Data Path 821.At that time, the destination module may asserts an acknowledge signaland send it to the Register and Control Module 820. The destinationmodule will hold the acknowledge signal true until it detects the readstrobe from the Register and Control Module 820 going false. TheRegister and Control Module 820 may dual-rank synchronizes the returningacknowledge signal before making the decision to release the readstrobe. Once the read strobe is released, the Register and ControlModule 820 is able to perform another read or write transaction. It isimportant to note that the First and Second Control Data Path 821 and822 may use various types of handshake control. A dedicated portion ofthe First and Second Data Path 821 and 822 may be used exclusively forany of the address, data, and control signals or may be used in amultiplexed fashion depending on the desired design and systemperformance criteria. An alternate embodiment of Register and ControlModule 820 includes a dedicated point-to-point read data bus and adedicated party-line write data bus that are implemented between theRegister and Control Module 820 and the Digital Image Processing System800 modules via the First and Second Control Data Path 821 and 822. Thefollowing paragraphs describe the operation of the Output Module 840.

An exemplary electronic display panel may comprise many regions and eachof which is independently driven. Therefore as many output displaymodules (ODM) as display regions are required, where each ODM retrieves,processes, and outputs onto the Output Display Data Path 846 theprocessed video data information for its designated display region. Inaccordance with one embodiment, the architecture of the Digital ImageProcessing System 800 is developed with the ability to drive a largedisplay panel that comprises sixteen display regions. In order toprovide such a flexible system architecture to be used with varioustypes of electronic display panels, a unique and programmable designfeatures are implemented within each ODM. One of the ODM design featuresis that each ODM comprises identical programmable circuitry, where eachODM can be programmed, e.g. enumerated using sequential numbers 0, 1, 2. . . , such that only one of the ODMs will behave as a Master ODM andall of the others will behave like Slave ODMs. One of the functions ofthe Master ODM is to control and insure that the starting point of theVertical and Horizontal sync signals is the same for all of the ODMs. Inaddition, the master ODM further controls and intervenes in themultiplexing of the data being read from specific registers within eachof the Slave ODMs through the First Control Data Path 821. Any of theODMs comprises the circuitry to operate as a Master ODM if it isprogrammed as such. Therefore, the ability to scale the Digital ImageProcessing System 800 to drive large number of display regions with asmany numbers of ODMs is greatly enhanced by the simple functionalability to enumerate each ODM and program its functionality. Someadditional advantages are gained when scaling the Digital ImageProcessing System 800 such as: (i) a reduction of the amount of timerequired to test the Output Module 840 and to verify the functionalityof each ODM, and (ii) correct routing of each ODM within the overallDigital Image Processing System 800.

The Output Module 840, as shown in FIG. 8A, comprises multipleindependent output display modules, namely ODM_(—)1 841, ODM_(—)2 842,ODM_(—)3 843, ODM_(—)4 844, and ODM_k 845. Each of the ODMs is capableof accessing and independently retrieving, from Memory 850, video datainformation of a digital image having a known starting memory locationand a first width and height. The digital image may constitute aportion, or the entirety, of the input digital image as captured by theInput Module 810. Each of the ODMs outputs onto the Output Display DataPath 846 a processed digital image that corresponds to the retrieveddigital image from Memory 850. For example, a Quad HD electronic displaypanel, Monitor 695 as shown in FIG. 6A, comprises four identical displayregions each with a predefined resolution and a second width and height.In one embodiment, any of the display regions may be specified using adifferent resolution and a different width and height for each region.Therefore, each output display module, e.g. ODM_(—)1, can be programmed,independently from other ODMs, to process the retrieved digital imageand to display it exclusively in accordance with the requirement of thedisplay region that the output display module is assigned to drive, e.g.resolution, width and height, video format, or mixing other digitalimage input. Normally, the display region width and height have largerdimensions as defined by the second width and height, than the retrieveddigital image from Memory 850 as defined by the first width and height.Usually, the horizontal scaling ratio of the second width divided by thefirst width is equal to the vertical scaling ratio of the second heightdivided by the first height such that the aspect ratio of the digitalimage is kept constant.

A horizontal or vertical scaling ratio of one indicates that the outputresolution in the specified dimension, i.e. horizontal or vertical, isthe same as the input resolution and no scaling takes place. However,each of the ODM_(—)1 841, ODM_(—)2 842, ODM_(—)3 843, ODM_(—)4 844, andODM_k 845 comprises programmable circuitry capable of processing andscaling the retrieved digital image using an arbitrary horizontalscaling ratio and an arbitrary vertical scaling ratio, that do notnecessarily need to be equal. This is especially beneficial inprocessing digital images using various video format standards that mayspecify different vertical and horizontal resolutions. Thus, differentvertical and horizontal scaling ratios are used in order to properlyprocess and display the digital image using the specified display regionresolution. This is illustrated in the following example. A firstdigital image with a resolution of 720×480 is to be displayed using thedisplay region, Monitor 660 as shown in FIG. 6A, having a resolution of1440×960. Thus, both the horizontal and vertical scaling ratios equal totwo, and the processing of the digital image includes same scaling inthe horizontal and vertical directions. Similarly, if a second imagehaving a resolution of 360×480 and it is to be displayed using the fulldisplay region, Monitor 660, then it becomes apparent that thehorizontal scaling ratio is equal to four (1440 divided by 360), and thevertical scaling ratio is equal to two (960 divided by 480). Therefore,the processing of the second digital image includes different scaling inthe horizontal and vertical directions and the processed second digitalimage is displayed using the full display region resolution of 1440×960.Furthermore, the output display modules can be programmed to process andscale digital images using non-integer vertical and horizontal scalingratios, e.g. a horizontal scaling ratio of 2.5 may be used while avertical scaling ration of 1.5 may be used.

Various types of electronic display monitors with multiple definedregions may be coupled to the Output Display Data Path 846 to receiveand to display the processed video data information of the digitalimages processed by each of the output display modules. Furthermore, anelectronic display monitor may comprise an arbitrary number of displayregions as may be specified by M rows and N columns e.g. see FIGS. 7A,7B and FIG. 9A, where the total number of regions can be represented byM rows times N columns. Hence, the Output Module 840 would compriseODM_(—)1 through ODM_k output display modules, where k=M×N. The ODM_krepresents the k^(th) output display module that outputs, onto theOutput Display Data Path 846, a k^(th) processed digital image to bedisplayed via the k^(th) region of the electronic display panel. TheOutput Display Data Path 846 may comprise a single dedicated channel foreach of the display regions of the electronic display panel.Alternatively, a common channel may be used where processed video datainformation is tagged with the destination address of any one of theregions of the electronic display monitor. A Quad HD display panel is anexemplary electronic display panel with M=2 and N=2 and is used in thefollowing paragraphs to describe in further details the operation of theOutput Module 840, see FIG. 6A and FIG. 8A.

In accordance with one embodiment, the Output Display Data Path 846comprises four independent channels. Each channel is used to couple oneof the output display modules, namely ODM_(—)1 841, ODM_(—)2 842,ODM_(—)3 843, and ODM_(—)4 844, to one of the regions of the electronicdisplay panel Monitor 695, namely Monitor 660, Monitor 670, Monitor 680,and Monitor 690. Each of the ODM_(—)1 841, ODM_(—)2 842, ODM_(—)3 843,and ODM_(—)4 844 comprises identical circuitry and independentlyretrieves and processes a designated portion of the Image 610, namelythe Split 620, Split 630, Split 640, and Split 650 respectively, asdescribed above and in FIG. 6A. The output display module ODM_(—)1 841processes and outputs, onto its dedicated channel of the Output DisplayData Path 846, the video data information of the processed portion ofthe Split Image 620. The Monitor 660 receives and displays the videodata information of the processed portion of the Split Image 620 via theOutput Display Data Path 846. Similarly, each of the ODM_(—)2 842,ODM_(—)3 843, and ODM_(—)4 844 retrieves and processes the Split 630,Split 640, and Split 650 respectively. Furthermore, each of the ODM_(—)2842, ODM_(—)3 843, and ODM_(—)4 844 then outputs, onto its dedicatedchannel of the Output Display Data Path 846, the video data informationof the processed Split Image 630, Split 640, and Split 650,respectively. The Monitor 670, Monitor 680, and Monitor 690 receive anddisplay the video data information of the processed Split Image 630,Split 640, and Split 650 respectively. The overall image displayed onMonitor 695 corresponds to the original Image 610.

The Input Module 810, in accordance with one embodiment, is shown inFIG. 8D. The architecture of Input Module 810 comprises “k” instances ofthe Input Module 810 as shown in FIG. 8B. Input capture modules, namelyInput Capture_(—)1 830_(—)11, Input Capture_(—)2 830_(—)12, InputCapture_(—)3 830_(—)13, Input Capture_(—)4 830_(—)14, and InputCapture_k 830_(—)15 (to be referred to as ICMs) are used to capturevideo data information of transferred digital images via the DigitalInput Data Path 811. A single or multiple digital images sources may beused to output their respective digital images onto the Digital InputData Path 811, which may comprise a dedicated channel for each source ora common channel for all sources. Whatever technique is used it must beable to sustain the amount of video data information to be transferredas may be desired or specified by the Digital Image Processing System800. The architecture of the Input Module 810 shown in FIG. 8D providesthe ability to (i) increase the input capture bandwidth, (ii) receivemultiple digital images from multiple sources via the Digital Input DataPath 811, (iii) split a captured digital image into multiple regions,and (iv) accommodate the simultaneous capturing and processing ofdigital images having different video format. The captured video datainformation is processed using Video Formatter_(—)1 830_(—)21, VideoFormatter 2_(—)830_(—)22, Video Formatter 3_(—)830_(—)23, VideoFormatter 4_(—)830_(—)24, and Video Formatter_k 830_(—)25. Each of thevideo formatter modules comprises circuitry to receive video datainformation from their correspondent ICM, i.e. the Input Capture_(—)1830_(—)11, Input Capture_(—)2 830_(—)12, Input Capture_(—)3 830_(—)13,Input Capture_(—)4 830_(—)14, and Input Capture_k 830_(—)15respectively. Each of the video formatter modules functions in a similarfashion to the Video Formatter 810_(—)20 shown in FIG. 8B and describedabove. The continuous increase in demands for higher resolution digitalimages provide the needs to have a flexible architecture for the DigitalImage Processing System 800 to meet such demands, and any new additionalrequirements as it may become necessary, e.g. a different or a newlydeveloped video format standards. In accordance with one embodiment,each of the ICMs is used to capture a predetermined portion of an inputdigital image, where each portion is then processed and stored in Memory850 using the corresponding memory interface module. The memoryinterface modules, Memory Interface_(—)11 830_(—)31, MemoryInterface_(—)2 830_(—)32, Memory Interface_(—)3 830_(—)33, MemoryInterface_(—)4 830_(—)34, and Memory Interface_k 830_(—)35, function ina similar fashion to the Memory Interface 810_(—)30 module shown in FIG.8B and described above. The following paragraphs provide a descriptionof the operation of the Memory Data Path Controller 830.

The Memory Data Path Controller 830, the First Memory Data Path 831, andthe Second Memory Data Path 832 design requirement is to efficientlytransfer large amounts of data between the various modules of DigitalImage Processing System 800, e.g. between the Input Module 810 and theOutput Module 840, and the Memory 850. Control and video datainformation are pipelined together and thus pipeline stages can be addedto achieve timing closure especially when the Digital Image ProcessingSystem 800 is being manufactured as a System-on-Chip or SoC. In thiscase, large amount of data must be transferred relatively long distancesthroughout the SoC. Arbitrary numbers of pipeline stages between theMemory Data Path Controller 830 and Digital Image Processing System 800modules can be added without affecting the performance. The Memory DataPath Controller 830 is designed to accommodate and respond to differentmodes of operation for each of the internal modules of Digital ImageProcessing System 800, and thus enabling efficient and high performanceaccess to and from the Memory 850 using both the First and Second MemoryData Path 831 and 832 respectively. Each module can store or retrievedata from the Memory 850 in the most efficient format for its dataprocessing or type usage, thus further enabling the ability to scale theDigital Image Processing System 800 to meet the demands for a higherinput bandwidth, e.g. higher resolution or number of input sources, andlarger number of output display regions. For example, a digital imagerepresenting a two-dimensional graphics may be digitized and use alinear memory addressing for transferring its video data information inand out of Memory 850, while compressed digital images, e.g. MPEG, mayutilize a specific block memory addressing. The Memory Data PathController 830 is designed and capable of operating with at least fiveexemplary different modes (i) progressive scan macro block xy mode, (ii)interlaced scan macro block xy mode, (iii) progressive scan linear xymode, (iv) interlaced scan linear xy mode, and (v) sequential accessmode. Furthermore, the architecture of the Memory Data Path Controller830 includes a specialized memory organization design that allocatesregions of memory locations within the Memory 850 for the exclusive usewith certain types of video data information.

Each of the internal modules of Digital Image Processing System 800generates and outputs, onto the First Memory Data Path 831, memory writeor read commands that comprise an operation mode, a base index, and adigital image's location and size information. The location of thedigital image within Memory 850 may be determined using a startingmemory location that corresponds to the location of a first pixel ororigin of the digital image, e.g. top-leftmost pixel. Using the firstmemory location of a memory region as an origin, then an offset numberof memory locations from the first memory location may be used as wellto indicate the starting memory location of a desired digital image. Thedigital image's size information is identified with width, height, orthe total number of memory locations used within Memory 850. The MemoryData Path Controller 830 operates and responds to different modes thatutilize different location and size information as it may be necessaryfor the efficient transfer of the video data information from and toMemory 850, as is described later see FIGS. 10A and 10B. Consequently,the Memory Data Path Controller 830 initiates memory device write orread transactions in response to memory write or read commands using theoperation mode, base index, and the digital image's location and sizeinformation embedded in the memory write or read command. The MemoryData Path Controller 830 generates memory device write or read commandsand completes the Memory 850 device write or read transactions bysending or receiving video data information, from Memory 850 via theSecond Memory Data Path 832. The Memory Data Path Controller 830appropriately receives or forwards the video data information to themodule that issued the memory write or read command via the First MemoryData Path 831. The Digital Image Processing System 800 internal modulescan make successive back-to-back memory write or read requests thatinclude completely different mode of operation, base index, and imagesize and location. The Memory Data Path Controller 830 can handle thesememory device write or read transactions of entirely different types byappropriately arbitrating between the various modules of the DigitalImage Processing System 800 using the First Memory Data Path 831, andthe Memory 850 via the Second Memory Data Path 832. The memorysub-system Memory 850 is described further in the following paragraphs.

The Memory 850 device may be a single memory device or a memory systemcomprising multiple memory devices or modules, e.g. Memory 851 andMemory 852 as may be desired or necessary by the Digital ImageProcessing System 800. The Memory 850 is organized into multipleregions, where each region is specified using a starting memory locationbase address and a predefined number of memory locations. In onepreferred embodiment, the Memory 850 is organized into one hundredtwenty eight memory regions. In general, the Input Module 810 writes theinput digital image video data information into one or more memoryregions within Memory 850. The input Module 810 is also capable ofsplitting the input digital image into smaller regions each of which isstored into a separate memory region within Memory 850. The OutputModule 840 reads and processes the video data information as specifiedusing location and size information of a desired digital image from oneor more regions within Memory 850. For example, in accordance with a YUVvideo format standard, the ODM_(—)1 841 module reads the Y-component andUV-component of the video data information from a first and secondmemory region, respectively. The overall storage capacity of Memory 850is based on the application and overall processing requirement of videodata information of the Digital Image Processing System 800. The storagecapacity of each region of Memory 850 is dependent on the resolution,and the type of video data information for a given video format standardbeing used. Furthermore, various types of memory, e.g. DRAM, SRAM, DDR,etc. . . . , may be used to manufacture Memory 850 as an integratedcomponent within the Digital Image Processing System 800 or as astandalone memory system. In general, the Memory 850 must meet theoverall performance and timing requirement of the Input Module 810 andthe Output Module 840. The ability to use a particular organization ordesign of a memory system is influenced by the required overallperformance of Memory 850, and the engineering requirement to manage thecapacity and location of each of the memory regions within Memory 850.In accordance with one embodiment, each memory region's capacity andlocation is programmable and can be redefined for a given application'smemory usage requirements. The programming of the appropriate registerswith a new memory region's size and location within Memory 850, i.e.number of memory words and starting base address, provides a flexiblearchitecture for a scalable and manageable Memory 850 system. The MemoryData Path Controller 830 stores the base address for each memory regionin a look up table, where each base address is looked up using the baseindex embedded within the memory write or read command. Thus, using abase index eliminates the need to reprogram the various modules ofDigital Image Processing System 800 with a new set of base addresses,whenever a new organization or reallocation of the memory regions ofMemory 850 has taken place. Different storage and lookup means may beused for the base addresses of memory regions of Memory 850 e.g. fileregisters, programmable registers, Random Access Memory (RAM), orContent Addressable Memory (CAM).

An exemplary Digital Image 900, with a resolution of 48×32, is splitinto six regions Region_(—)1 911, Region_(—)2 912, Region_(—)3 913,Region_(—)4 914, Region_(—)5 915, and Region_(—)6 916 as shown in FIG.9A. The Digital Image 900 comprises thirty-two lines, where each lineextends in the horizontal direction and comprises 48 pixels. The words“line” or “row” may be used interchangeably to indicate an array ofpixels organized in the horizontal direction, video data informationthat corresponds to an array of pixels organized in the horizontaldirection, or may indicate a horizontal array of memory locationscomprising video data information that corresponds to a horizontal arrayof pixels. Similarly, the words “column” or “Col” are used to describean array of pixels, video data information, or memory locations but inthe vertical direction. Multiple video format standards may be used forthe video data information that corresponds to each pixel, e.g. 24 bitRGB or YUV 4:2:2, 16 bits, see above. The exemplary Digital Image 900comprises 32 lines and each line comprises 48 pixels, as shown in FIG.9B, where the first line (or line 0) is shown as Row_(—)0 900_(—)300,and the thirty-second line is shown as Row_(—)31 900_(—)331. Similarly,the first columns of pixels is shown as Col_(—)0 900_(—)400, and theforty-eighth column of pixels is shown as Col_(—)48 900_(—)448.Furthermore, a first starting pixel Pixel_(—)0 900_(—)0000 is shown atthe top-leftmost corner of the Digital Image 900, and is located at theintersection of the vertical position Row_(—)0 900_(—)300 and thehorizontal position Col_(—)0 900_(—)400. Similarly the last pixel of theDigital Image 900 is Pixel_(—)1535 900_(—)1535 and is shown at thebottom-rightmost corner of the Digital Image 900, and is located at theintersection of the vertical position Row_(—)31 900_(—)331 and thehorizontal position Col_(—)48 900_(—)448. In this example, each of thesix regions of Digital Image 900 is defined to have identical dimensionsof width and height that corresponds to sixteen pixels per side. Forexample, Region_(—)1 911 and Region_(—)2 912 each has a firsttop-leftmost pixel that is identified in reference the Digital Image 900as Pixel_(—)0 900_(—)0000 and Pixel_(—)16 900_(—)0016. Furthermore, thefirst top-leftmost pixel of Region_(—)1 911 is identified withinRegion_(—)1 911 as Pixel_(—)0 911_(—)000. Similarly, the firsttop-leftmost pixel of Region_(—)2 912 is identified within Region_(—)2912 as Pixel_(—)0 912_(—)000. As each region of Digital Image 900 isindependently read or written, it becomes important to have labels forthe elements of each region in reference to itself as well as theDigital Image 900, see FIG. 9C through FIG. 9P.

Digital Image 900 has a resolution that corresponds to a total number of1536 pixels and total number of memory allocation of 36,864 bits (1536times 24) for a 24 bit RGB or 24,576 bits (1536 times 16) for YUV 4:2:2video format. In the following examples, certain assumptions areprovided as an exemplary mean to describe some of the operation ofDigital Image Processing System 800. The video format standard of YUV4:2:2, 16 bits per pixel is used to store the processed video datainformation of the captured Digital Image 900. Hence, video datainformation for one pixel use 8-bits to store the Y-component andanother 8-bits for the UV-component. An exemplary 64-bit-word isallocated to each memory location within a first and second region ofMemory 850. Hence, the Digital Image 900 would require 384 memorylocations to store all of the video data information in accordance withYUV 4:2:2 16 bits video format, organized as 192 memory locations foreach of the Y-component and UV-component of the captured Digital Image900 within the first and second region of Memory 850 respectively. Anexemplary first base address of (00001024)₁₀ is used to indicate theactual physical address of the first starting memory location, MemoryLocation 0 (Row_(—)0, Col_(—)0) 900 _(—)800 as shown in FIG. 9D, of thefirst region within Memory 850 where the Y-component of the video datainformation is to be stored. Similarly, an exemplary second base addressof (00004096)₁₀ is used to indicate the actual physical address of thefirst starting memory location of the second region within Memory 850where the UV-component of the video data information is to be stored.Input Module 810 captures and processes the video data information ofDigital Image 900 into a first quadrangle digital image comprising theY-component and a second quadrangle digital image comprising theUV-component. An expanded view of the Region_(—)1 911 is shown in FIG.9C. An exemplary memory organization of Digital Image 900 is shown inFIG. 9D, where repeated references to FIG. 9A through 9P will be used inthe following paragraphs. The first eight pixels of the Region_(—)1 911,starting with Pixel_(—)0 911_(—)000 and ending with Pixel_(—)7911_(—)007, form a first starting Pixel Group 0 911_(—)500 where theY-component of the video data information is stored into Memory Location0 900_(—)800, as shown in FIG. 8C and FIG. 8D.

In accordance with one embodiment, the Input Module 810 initiates atleast one memory transaction request to transfer and store theY-component of the video data information of Pixel_(—)0 900_(—)0000through Pixel_(—)1535 900_(—)1535 in the first memory region withinMemory 850. Similarly, Input Module 810 initiates at least one memorytransaction to transfer the UV-Component of the video data informationof all the pixels of Region_(—)1 911, Region_(—)2 912, Region_(—)3 913,Region_(—)4 914, Region_(—)5 915, and Region_(—)6 916 to be stored inthe second memory region within Memory 850. In this example, it ispossible for the Y-component of video data information for eight pixelsto be stored using a single 64-bit word or one memory location, asdescribed above and shown in FIG. 9C and FIG. 8D. Furthermore, a FirstMemory Block 911_(—)800, as illustrated by the region enclosed withindashed lines in FIG. 9D, represents the Y-component of the video datainformation of all the pixels within Region_(—)1 911, i.e. Pixel_(—)0911_(—)000 through Pixel_(—)255 911_(—)255 as shown in FIG. 9C.

The memory organization of the First Memory Block 911_(—)800 is shown inFIG. 9D. The overall Y-Component of the video data information ofRegion_(—)1 911 of Digital Image 900 is stored sequentially from left toright using sixteen rows Row_(—)0 900_(—)300 through Row_(—)15900_(—)315, and two columns, Col_(—)0 900_(—)480 and Col_(—)1900_(—)481. The first region of Memory 850 comprises a first startingMemory Location 0 (Row_(—)0, Col_(—)0) 900 _(—)800, located at theintersection of a first vertical position corresponding to Row_(—)0900_(—)300, and a first horizontal position corresponding to Col_(—)0900_(—)480. As has been described earlier, the first starting MemoryLocation 0 900_(—)800 comprises the Y-component of the video datainformation of the first starting Pixel Group 0 911_(—)500 comprisingthe first eight pixels of the first line Row_(—)0 911_(—)300 ofRegion_(—)1 911 of Digital Image 900. Similarly, Memory Location 1 (Row0, Col_(—)1) 900_(—)801 comprises the Y-component of the video datainformation of the next and last eight pixels (from left to right) ofthe first line Row_(—)0 911_(—)300 of Region_(—)1 911. The second lineof Region_(—)1 911 comprises the first 16 pixel of the second lineRow_(—)1 900_(—)301 of Digital Image 900, while the second line ofRegion_(—)3 913 comprises the last 16 pixel of the second line Row_(—)1900_(—)301 of Digital Image 900, and so on as shown in FIG. 9D.

Another exemplary memory location is located at the intersection ofRow_(—)0 900_(—)300 and Col_(—)5 900_(—)485, i.e. Memory Location 65(Row 0, Col_(—)5) 900_(—)865, comprising the Y-component of the videodata information of the last eight pixels of the first line Row_(—)0900_(—)300 of the Digital Image 900 as shown in FIG. 9D. In this case,these last eight pixels are also the last eight pixels of the first lineof Region_(—)3 913 of the Digital Image 900.

The First Memory Block 911_(—)800 comprises thirty-two memory locations,zero through thirty-one, as shown in FIG. 9D. The first starting MemoryLocation 0 (Row_(—)0, Col_(—)00) 900_(—)800 is accessible using thefirst base address that corresponds to the starting memory location ofthe first region within Memory 850, i.e. (00001024)₁₀. Similarly, anyother memory location within any one of the Region_(—)1 911, Region_(—)2912, Region_(—)3 913, Region_(—)4 914, Region_(—)5 915, and Region_(—)6916 may be accessed using a corresponding row and column number thatcorrespond to the intersection of a vertical and horizontal positionwithin Digital Image 900. For example, the first starting memorylocation of Region_(—)3 913 is Memory Location 64 and is located at aphysical address that is to be found at an offset address of(00000064)₁₀ from the base address (00001024)₁₀ of the first region ofMemory 850. Hence, the physical address of the first starting memorylocation of Region_(—)3 913 is located at an address equal to the sum ofthe base address and the offset address, i.e. (00001088)₁₀.Subsequently, a physical address of (00001089)₁₀ would corresponds toMemory Location 65 (Row_(—)0, Col_(—)5) 900_(—)865, as shown in FIG. 9D.It should be noted that different granularity of memory access isaccomplished using longer or shorter words, e.g. 128-bit words foraccessing sixteen pixels at a time or 16-bit words for accessing twopixels at a time. The access granularity of Memory 850 influences theperformance of the Digital Image Processing System 800. For a givenapplication, various access granularity of Memory 850 can be used toaccommodate a certain performance specification. Each of the video datainformation of Region_(—)2 912, Region_(—)3 913, Region_(—)4 914,Region_(—)5 915, and Region_(—)6 916 is organized and stored into thefirst memory region as shown in FIG. 9D.

In accordance with another embodiment, independent memory regions ofMemory 850 are used to store each of the video data information ofRegion_(—)1 911, Region_(—)2 912, Region_(—)3 913, Region_(—)4 914,Region_(—)5 915, and Region_(—)6 916 independently. Similarly, eachmemory region may be accessed independently from other memory regions,and the retrieved video data information is processed, manipulated, anddisplayed, using a display region, in accordance with a video effect,resolution, scaling or video format that may be different from what isdesired or required by another display region. Various memoryorganization methods and techniques may be used for how the regionswithin the Memory 850 are allocated. Accordingly, Memory 850organization may change with the capacity or type of the physical memorybeing used. Furthermore, how fast the video data information is to beprocessed, stored, or retrieved would have an implication on the optimumorganization of Memory 850. For example, the video data information ofRegion_(—)1 911 may be stored sequentially in a linear fashion usingRow_(—)0 900_(—)300 through Row_(—)5 900_(—)305, such that the firststarting Memory Location 0 900_(—)800 is still located at theintersection of Row_(—)0 900_(—)300 and Col_(—)0 900_(—)480. However,the memory location 31 is now located at the intersection of Row 5900_(—)305 and Col_(—)1 900_(—)481. In the following paragraphs,exemplary video data information transfers into, and out of Memory 850is described; please refer to FIG. 8A, FIG. 8B, FIG. 9A, through FIG.9D.

The Input Module 810 comprises a first and second programmable registersto store a first and second value that corresponds to the Digital Image900 Width 900_(—)612 and Height 900_(—)622, respectively. The InputModule 810 comprises Input Capture 810_(—)10 to receive and extract theDigital Image 900 video data information via the digital input datapath, in accordance with the Digital Image 900 video format, e.g. 24 bitRGB. The Input Capture 810_(—)10 may also be programmed to receive andextract only a predefined region's video data information, e.g.Region_(—)1 911 of the Digital Image 900. Region_(—)1 911 is definedusing a starting first pixel location Pixel_(—)0 911_(—)000, its Width911_(—)612 and Height 911_(—)622 within Digital Image 900. The InputModule 810 comprises Video Formatter 810_(—)20 that processes thecaptured video data information and generates, in accordance with asecond video format e.g. YUV 4:2:2 16 bits, the video data informationthat corresponds to the Y-component and UV-component of Digital Image900.

The Input Module 810 further comprises Memory Interface 810_(—)30comprising a third and fourth programmable registers to store a firstand second base index values, e.g. (001)₁₀ and (002)₁₀. The first andsecond base index values are used as pointers to the first and secondbase addresses, e.g. (00001024)₁₀ and (00004096)₁₀ of the first andsecond regions of Memory 850, as described above. This provides theflexibility to reorganize Memory 850 as needed. For example, aparticular desired performance of the Digital Image Processing System800 is satisfied by redefining or reprogramming the base addresses ofmemory regions, without affecting other memory access requestsparameters. The Memory Interface 810_(—)30 generates and outputs ontothe First Memory Data Path 831 at least one first memory write commandto transfer the Y-component of the video data information of DigitalImage 900 starting at Memory Location 0 900_(—)800 of the first regionof Memory 850. In this example, the Memory Location 0 is used to storethe Y-component of the video data information of the first startingpixel, Pixel_(—)0 900_(—)0000 which is the top-leftmost pixel of theDigital Image 900. A description of memory access request to Memory 850provides more details about the generation of a memory write or readcommand or a memory device write or read command.

The first memory write command comprises the first Base Index 1020 value(001)₁₀, and a memory Offset Address 1070 value of (000)₁₀, see FIG. 10Aand FIG. 10B. The Offset Address 1070 is used to indicate that theMemory Location 0 900_(—)800 is to be stored at the memory location asindicated by the first base address (00001024)₁₀ since the offsetaddress is zero in this case. Since all of the Y-component of video datainformation of Region_(—)1 911, i.e. Pixel_(—)0 911_(—)000 throughPixel_(—)255 911_(—)255, are grouped in eight pixels per memorylocation, then the total number of 64-bit words required is thirty-two.Thus, the first memory write command further comprises a total number ofmemory locations, #Words 1080, value of (032)₁₀. The #Words 1080 is usedto indicate how many words or memory locations are to be transferredfrom the Input Module 810, in response to the first memory writecommand, to the Memory Data Path Controller 830 via the First MemoryData Path 831.

In another embodiment, the first memory write command comprises verticaland horizontal memory position of the first starting memory location ofRegion_(—)1 911, i.e. Ystart 1030 that corresponds to Row_(—)0900_(—)300 and Xstart 1040 that corresponds to Col_(—)0 900_(—)480, theintersection of Xstart 1040 and Ystart 1030 corresponds to MemoryLocation 0 900_(—)800. The first memory write command further comprisesthe width, Xcount 1050, and height, Ycount 1060, of Region_(—)1 911 interms of memory words. In this example, the Width 911_(—)612 ofRegion_(—)1 911 is 16 pixels and corresponds to two 64-bit memory words.The Height 911_(—)622 of Region_(—)1 911 is 16 lines and thuscorresponds to sixteen rows of 64-bit memory words, Row_(—)0 911_(—)300through Row15 911_(—)315, see FIG. 9C.

In one embodiment, the Memory Interface 810_(—)30 of the Input Module810 issues multiple memory write commands, as described above, to effectthe transfer of all of the Y-component of the video data information ofRegion_(—)1 911 to the Memory Data Path Controller 830 via the FirstMemory Data Path 831. Similarly, Memory Interface 810_(—)30 transfersthe UV-component of the video data information of Region_(—)1 911 ofDigital Image 900 to the second region of Memory 850. The MemoryInterface 810_(—)30 generates and outputs onto the First Memory DataPath 831 one, or multiple, second memory write command in accordancewith the description of above paragraphs.

The Memory Data Path Controller 830 comprises a First Memory Interface830_(—)10 that receives the first memory write command and theY-component of the video data information via the First Memory Data Path831. The Memory Data Path Controller 830 further comprises logiccircuitry to extract from the first memory write command the first BaseIndex 1020 value (001)₁₀, the memory Offset Address 1070 value of(000)₁₀, and the total number of memory locations, #Words 1080, value of(032)₁₀. In one embodiment, the Memory Data Path Controller 830 furthercomprises logic circuitry to extract from the first memory write commandthe vertical and horizontal position of the first starting memorylocation of Region_(—)1 911, and the width and height information. Inthis example, width value Xcount 1050=(002)₁₀, the height value Ycount1060=(016)₁₀, Ystart 1030=(000)₁₀ and Xstart 1040=(001)₁₀, see above.

The Memory Data Path Controller 830 generates the first base address ofthe first memory region within Memory 850 based on the extracted firstbase index, Base Index 1020. The Second Memory Interface 830_(—)30generates the appropriate physical memory address by using the firstbase address and the memory offset address, Offset Address 1070. TheSecond Memory Interface 830_(—)30 further generates at least one, ormultiple, first memory device write command to complete the transfer ofthe Y-component of the video data information of Region_(—)1 911 to thefirst region of Memory 850 via the Second Memory Data Path 832. In thisexample, the first memory device write command includes the memoryaddress (00001024)₁₀ as the first starting memory location address,where the Y-component of the Memory Location 0 900_(—)800 is to bestored. The content to be stored in the first memory region of Memory850 in response to the first memory device write command, starting atphysical memory address of (00001024)₁₀, corresponds to the Y-componentof the video data information of Region_(—)1 911. This includes MemoryLocation 0 (Row_(—)0, Col_(—)00) 911_(—)800 that corresponds to PixelGroup 0 911_(—)500 through the Memory Location 31 that corresponds toPixel Group 31 911_(—)531, see Fig. C.

In one embodiment, the Second Memory Interface 830_(—)30 generates atleast one, or multiple, first memory device write command to completethe transfer of the Y-component of the video data information of DigitalImage 900 to the first region of Memory 850 via the Second Memory DataPath 832. The first memory device write command provides all thenecessary control and/or handshake information for Memory 850 toproperly decode the first memory device write command and store theY-component of the video data information of Digital Image 900 inresponse to the first memory device write command. The stored content inthe first memory region of Memory 850, starting at physical memoryaddress of (00001024)₁₀, corresponds to the Y-component of the videodata information of Digital Image 900, Memory Location 0 (Row 0,Col_(—)0) 911_(—)800 through the Memory Location 191 (Row_(—)31,Col_(—)5) 911_(—)191. The Memory Data Path Controller 830 furthercomprises Control 830_(—)20 module to control and manage the transfer ofthe video data information flow received via the First Memory Data Path831 and outputted to Memory 850 via the Second Memory Data Path 832. Thetransfer of the UV-component is described in the following paragraphs.

Similarly, the First Memory Interface 830_(—)10 receives the secondmemory write command and the UV-component of the video data information,to be transferred in response to the second memory write command, viathe First Memory Data Path 831. The logic circuitry extracts at leastthe second base index information, the starting Memory Location 0, andthe total number of memory locations from the second memory writecommand. In accordance with the same process as described above, theMemory Data Path Controller 830 generates the second base address basedon the second base index. Furthermore, The Second Memory Interface830_(—)30 generates at least one, or multiple, second memory devicewrite command to complete the transfer of the UV-component of the videodata information of Digital Image 900 to the second region of Memory 850via the Second Memory Data Path 832 in response to the second memorywrite command. The Control 830_(—)20 module controls and manages thetransfer of the UV-component of the video data information flow receivedvia the First Memory Data Path 831 and outputted to Memory 850 via theSecond Memory Data Path 832. The output display modules retrieve thevideo data information from Memory 850 for further processing as isdescribed in the following paragraphs.

In one embodiment, the output display module ODM_(—)1 841 is assigned toprocess the Y-component and the UV-component of the video datainformation from Region_(—)1 911. The other output display modules thatare part of the Output Module 840, e.g. ODM_(—)2 842, is programmed toprocess the Y-component and the UV-component of the video datainformation from Region_(—)2 912, and so on for the other ODMs. Each ODMprocesses one region of the Digital Image 900 and output the results toa dedicated display region of an electronic display panel. The combinedpicture resulting from all the adjoined display regions, comprising allthe processed regions of the Digital Image 900, results in a continuousand seamless display of Digital Image 900 as if it was processed by oneoutput display module. A block diagram of an exemplary output displaymodule is shown in FIG. 8E. Two-independent data paths are coupled tothe First Memory Data Path 831. Each of the data paths producesindependent access requests to Memory 850, as described below. Theoutput display module ODM_(—)1 841 further comprises a Control and DataInterface 841_(—)30 module that is coupled to the First Control DataPath 821 and to a Registers & Control 841_(—)40 module. The Control andData Interface 841_(—)30 enables access to ODM_(—)1 841 internalregisters and programmability control for ODM_(—)1 841 functions. TheRegisters & Control 841_(—)40 module comprises the necessary logiccircuitry to store data and control information, and provide properinterface to the internal modules of ODM_(—)1 841.

The first data path of output display module ODM_(—)1 841 comprises aFirst Input Buffer Control 841_(—)10. The Y-component of the video datainformation of Region_(—)1 911 is retrieved from Memory 850 using thefirst data path. Furthermore, the first data path comprises a verticalscaler module VS 841_(—)11 to process and/or scale in the verticaldirection the Y-component of the video data information from Region_(—)1911. An inter-scaler buffer ISB 841_(—)12 provides the necessarybuffering and management control of the streamed output of the verticalscaler VS 841_(—)11 and into a horizontal scaler HS 841_(—)13, whichprocesses or scales in the horizontal direction the already verticallyscaled Y-component of the video data information from Region_(—)1 911.Since the vertical processing or scaling occurs separately from thehorizontal processing or scaling, then the output display module iscapable to scale independently the retrieved video data information ineither the vertical or the horizontal direction. Similarly, the outputdisplay module ODM_(—)1 841 second data path comprises a Second InputBuffer Control 841_(—)20 that is assigned to retrieve the UV-componentof the video data information of Region 1 911 from Memory 850. Thevertical scaler VS 841_(—)21 processes or scales the UV-component of thevideo data information and output the vertically processed video datainformation to inter-scaler buffer ISB 841_(—)22. The horizontal scalerHS 841_(—)23 process or scale the already vertically processedUV-component of the video data information and output the horizontallyprocessed video data information to an Output Formatter 841_(—)50.

The horizontal scalers HS 841_(—)13 and HS 841_(—)23 stream theirprocessed video data information to the Output Formatter 841_(—)50 thatfurther process and recombine the already vertically and horizontallyprocessed or scaled Y-component and the UV-component of the video datainformation from Region_(—)1 911. The Output Formatter 841_(—)50 streamsits output onto the Output Display Data Path 846 via a dedicated channelto a designated display region. The Output Formatter 841_(—)50 processesthe video data information of Region_(—)1 911 in accordance with adesired output video format standard as specified by the designateddisplay region, e.g. RGB 4:4:4 24 bits per pixel. The output videoformat standard can be different from the YUV 4:2:2 16-bits used forstoring and processing the video data information of Region_(—)1 911 ashas been described above. The output display module ODM_(—)1 841functions are programmable to independently process or scales the videodata information in (i) the vertical direction, (ii) the horizontaldirection, and (iii) a designated output video format standard. Thisprovides for a proper display of the final processed video datainformation of Region_(—)1 911 in accordance with the intended displayregion of the electronic display panel.

An exemplary Memory Access Request 1000 structure to access the videodata information stored in Memory 850, as shown in FIG. 10A and FIG. 10B, describes alternate means for using necessary digital image size andlocation information to generate memory write or read commands. In thisexample, the video data information of Region_(—)1 911 comprisesthirty-two memory locations and is stored within the first region ofMemory 850, as shown in FIG. 9B, FIG. 9C, and FIG. 9D. The First InputBuffer Control 841_(—)10 produces a memory read command comprising aBase Index 1020 to read the video data information out of Memory 850.The Base Index 1020 corresponds to the first starting memory location ofthe first region of Memory 850, and in this example equals (001)₁₀. Thefirst memory read command further comprises a vertical origin Ystart1030 value that corresponds to Row_(—)0 900_(—)300, and a horizontalorigin Xstart 1040 value that corresponds to Col_(—)0 900_(—)400. Theorigin of Region_(—)1 911 is the top-left corner of the Digital Image900, as specified in this example by the starting Memory Location 0 (Row0, Col_(—)0) 911_(—)800. Xstart and Ystart values correspond to thevertical and horizontal location of a memory word comprising a firststarting pixel Pixel_(—)0 900_(—)0000. Furthermore, Xcount 1060 is thewidth in memory words (or memory locations) of the Region_(—)1 911 andin this example is specified as two 64-bit Words used for all sixteenpixels of one line of Region_(—)1 911. Ycount 1050 is the height inmemory rows or lines of the Region_(—)1 911 and in this example isspecified as sixteen lines. The first memory read command may furthercomprises other control bits and data, Control 1010, as may be necessaryto describe the type of video data information to be processed, how datainformation is organized in Memory 850, or signals as required by theMemory Data Path Controller 830 for proper execution of the memoryaccess request. In accordance with the structure of FIG. 10A and thisexample, the first memory read command would comprise: [Control bits],[(001)₁₀], [(000)₁₀], [(000)₁₀], [(016)₁₀], [(002)₁₀]. Another exemplaryfirst memory read command using an Offset Address 1070 of zero, sinceMemory Location 0 is actually stored at zero offset from the firststarting memory location of the first region of Memory 850. Furthermore,Regions_(—)1 911 comprises a total number of memory locations or 64-bitswords, #Words 1080, of 32, thus in accordance with the structure of FIG.10B, the first memory read command would comprise: [Control bits],[(001)₁₀], [(000)₁₀], [(032)₁₀]. Whichever structure is used for thememory read command the Memory Data Path Controller 830 decodes andresponds accordingly. In this example, the Memory Data Path Controller830 generates the bases address for the intended memory region by usingthe Base Index 1020 value of (001)₁₀ as a pointer in a lookup table toretrieve the corresponding base address, i.e. (00001024)₁₀. Furthermore,a memory device read command is generated using this base address andother information about location and size of the intended memorylocations to be read, in accordance with the necessary constraintsrequirement to access Memory 850. The Second Memory Interface 830_(—)30generates the location information for the address of the startingmemory location to be read out of Memory 850 as (00001024)₁₀ by using(i) the base address, in this example (00001024)₁₀, and (ii) the offsetaddress of the desired memory location, in this example (00000000)₁₀.Alternatively, the location information for the address of the startingmemory location to be read out of Memory 850 is generated by performingproper operation using (i) the base address, (ii) the vertical memorylocation pointer Ystart 1030, and (iii) the horizontal memory locationpointer Xstart 1040. In addition, The Second Memory Interface 830_(—)30generates the size information using #Words 1080 for total number ofmemory locations to be read, e.g. (00000032)₁₀. Alternatively, itgenerates the size information using the intended memory region sizegiven by the vertical number of rows Ycount 1050 and the horizontalnumber of columns Xcount 1060. Hence, in this example, the memory deviceread command is generated to indicate that the first memory location tobe read is at address (00001024)₁₀, and the last memory location to beread is at address (00001055)₁₀.

The following paragraphs describes the processing of a quadrangledigital image D_(—)1 981 by adding margin pixels to the Region_(—)1 911as shown in FIG. 9E. The generation of the margin pixels is accomplishedusing various means or the combination of various methods as has beendescribed above, please refer to embodiments as described above. Inaccordance with one embodiment, a Top Margin 981_(—)623 having a TopMargin Depth 981_(—)653 of one pixel is generated by replicating thevideo data information of the corresponding pixels of a Top Edge911_(—)732. Similarly, a Bottom Margin 981_(—)625 having a Bottom MarginDepth 981_(—)655 of one pixel is generated by replicating the video datainformation of the corresponding pixels of a Bottom Edge 911_(—)752. ALeft Margin 981_(—)626 having a Left Margin Depth 981_(—)656 of onepixel is generated by replicating the video data information of thecorresponding pixels of (i) the first pixel of the Top Margin981_(—)623, (ii) the pixels of a Left Edge 911_(—)762, and (iii) thefirst pixel of the Bottom Margin 981_(—)625. Similarly, a Right Margin981_(—)624 having a Right Margin Depth 981_(—)654 of one pixel isgenerated by replicating the video data information of the correspondingpixels of (i) the last pixel of the Top Margin 981_(—)623, (ii) thepixels of a Right Edge 911_(—)742, and (iii) the last pixel of theBottom Margin 981_(—)625. The chosen vertical and horizontal scalingprocesses, to provide the desired quality of the processed output image,influence the depth size of each of the Top Margin Depth 981_(—)653,Bottom Margin Depth 981_(—)655, Left Margin Depth 981_(—)656, and RightMargin Depth 981_(—)654. In accordance with one embodiment, a depth ofeight pixels is used. The quadrangle digital image D_(—)1 981 has awidth, D_(—)1 Width 981_(—)612, and a height, D_(—)1 Height 981_(—)622,in accordance with the following relationships:

D _(—)1 Width 981_(—)612=Left Margin 981_(—)626+Width 911_(—)612+RightMargin 981_(—)624  Eq. 5

D _(—)1 Height 981_(—)622=Top Margin 981_(—)623+Height 911_(—)622+BottomMargin 981_(—)625  Eq. 6

In accordance with one embodiment, The video data information content ofeach of the pixels within the Top Margin 981_(—)623, forming a new firstline of D_(—)1 981, are generated using a copy of the video datainformation of a corresponding pixel that is directly below it and is atthe Top Edge 911_(—)732. For example, the first pixel of the Top Margin981_(—)623 comprises the video data information of Pixel_(—)0911_(—)000, and the last pixel of the Top Margin 981_(—)623 comprisesthe video data information of Pixel_(—)015 911_(—)015.

Similarly, the video data information content of each of the pixelswithin the Bottom Margin 981_(—)625, forming a new last line of D_(—)1981, are generated using a copy of the video data information of acorresponding pixel that is directly above it and is at the Bottom Edge911_(—)752. For example, the first pixel of the Bottom Margin 981_(—)625comprises the video data information of Pixel_(—)240 911_(—)240, and thelast pixel of the Bottom Margin 981_(—)625 comprises the video datainformation of Pixel_(—)255 911_(—)255.

In accordance with one embodiment, the video data information content ofeach of the pixels within the Left Margin 981_(—)626, forming a newfirst column of pixels for D_(—)1 981, is generated using a copy of thevideo data information of a corresponding pixel that is directly to theright of it. For example, the top pixel of the Left Margin 981_(—)626comprises the video data information of the first pixel of the TopMargin 981_(—)623. The bottom pixel of the Left Margin 981_(—)626comprises the video data information of the first pixel of the BottomMargin 981_(—)625. The other pixels of the Left Margin 981_(—)626comprise the video data information of the pixels of the Left Edge911_(—)762.

Similarly, the video data information content of each of the pixelswithin the Right Margin 981_(—)624, forming a new last column of pixelsfor D_(—)1 981, is generated using a copy of the video data informationof a corresponding pixel that is directly to the left of it. Forexample, the top pixel of the Right Margin 981_(—)624 comprises thevideo data information of the last pixel of the Top Margin 981_(—)623.The bottom pixel of the Right Margin 981_(—)624 comprises the video datainformation of the last pixel of the Bottom Margin 981_(—)625. The otherpixels of Right Margin 981_(—)624 comprise the video data information ofthe pixels of the Right Edge 911_(—)742.

In the following paragraphs, the first data path of an output displaymodule, e.g. ODM_(—)1 841, is used to describe an exemplary vertical andhorizontal processing of the video data information for Region_(—)1 911as shown in FIG. 9C. In this example, the video data informationcorresponds to the Y-Component of the digital image that corresponds toRegion_(—)1 911 is processed using the first data path of ODM_(—)1 841,while the second data path processes in a similar fashion anindependently retrieved video data information. In the followingexample, a margin depth of one pixel is assumed for each of the TopMargin Depth 981_(—)653, Bottom Margin Depth 981_(—)655, Left MarginDepth 981_(—)656, and Right Margin Depth 981_(—)654, as shown in FIG.9E. Each of the Top Margin Depth 981_(—)653, Bottom Margin Depth981_(—)655, Left Margin Depth 981_(—)656, and Right Margin Depth981_(—)654 can be specified independently from each other. The margindepth can vary in order to meet a given design and specificationrequirement of the output display module. Furthermore, each of thehorizontal and vertical scaling ratios is assumed equal to one, whichmeans that the desired output image resolution is the same as theretrieved input image's resolution in both the vertical and horizontaldirections.

In accordance with one embodiment, the generation of the video datainformation of the pixels of the Top Margin 981_(—)623 is done on thefly. When the first line Row_(—)0 911_(—)300, as shown in FIG. 9C, isread out of memory and into the First Input Buffer Control 841_(—)10 asRow_(—)1 981_(—)301, as shown in FIG. 9E. The video data informationcontent of the pixels of Row_(—)0 911_(—)300 is copied or replicated togenerate Row_(—)0 981_(—)300, as shown in FIG. 9E, namely the Top Margin981_(—)623 of the quadrangle digital image D_(—)1 981.

Similarly, the generation of the video data information of the BottomMargin 981_(—)625 is done on the fly when the last line of Region_(—)1911, namely Row_(—)15 911_(—)315 see FIG. 9C, is read out of memory andinto the First Input Buffer Control 841_(—)10 as Row_(—)16 981_(—)316,see FIG. 9E. A simple process to copy the video data information of thepixels of Row_(—)15 911_(—)315 may be used to generate the Bottom Margin981_(—)625 that corresponds to the eighteenth line of D_(—)1 981, namelyRow_(—)17 981_(—)317.

Other processes or methods may be used as well to effect the generationof the pixels of the Top Margin 981_(—)623 and Bottom Margin 981_(—)625from pixels within Region_(—)1 911 or neighboring regions, e.g.Region_(—)2 912. Variety of methods as described above may be employedto generate the pixels of the Top Margin 981_(—)623 and Bottom Margin981_(—)625. Furthermore, various types of data filtering or datainterpolation can be used to process the video data information of thedesignated digital image and generate on the fly the video datainformation for the margin pixels. For example, video data informationof a specific color can be used to generate the video data informationof the pixels of the Top Margin 981_(—)623 and Bottom Margin 981_(—)625.

In this example, D_(—)1 Height 981_(—)622 comprises 18 lines and can becomputed using Eq. 6. For example, the sum of (i) the Top Margin981_(—)623 that comprises one line, (ii) Row_(—)0 911_(—)300 throughRow_(—)15 911_(—)315 comprising 16 lines, and (iii) the Bottom Margin981_(—)625 that comprises one line. At this stage, after the processingin the vertical direction is completed, the width of verticallyprocessed lines stored in the inter-scaler buffer ISB 841_(—)12corresponds to 16 pixels, and is the same as Width 911_(—)612, as shownin FIG. 9C.

The vertical scaler, VS 841_(—)11, operates using a group of two or morelines at a time to generate one vertically processed line that isoutputted to the inter-scaler buffer, ISB 841_(—)12, for temporarystorage. The number of lines that are used to produce one verticallyprocessed line depends on the type of scaling process methodology andthe number of coefficients required to provide a desired accuracy for agiven scaling process and/or a given scaling ratio for the intendedquality level of the scaled output image. In this example, the videodata information of the pixels of two vertically adjacent lines are usedto generate the video data information for the vertically processedline. In accordance with one embodiment, eight vertically adjacent linesare used to generate one vertically processed line that is outputted tothe inter-scaler buffer, ISB 841_(—)12, for temporary storage. Inaccordance with one embodiment, four vertically adjacent lines are usedto generate one vertically processed line that is outputted to theinter-scaler buffer, ISB 841_(—)12, for temporary storage. If thevertical scaling ratio is equal to two, then the total number of thevertically processed lines outputted to the inter-scaler buffer ISB841_(—)12 is twice that of D_(—)1 Height 981_(—)622. In this example,the vertical scaler VS 841_(—)11 would output thirty-six verticallyprocessed lines, which is twice that of the D_(—)1 Height 981_(—)622comprising eighteen lines, sixteen lines of which are from Region_(—)1911 and one line each from the Top Margin 981_(—)623 and Bottom Margin981_(—)625.

An exemplary processing of two vertically adjacent lines to produce onenew vertically processed line is described as follows; please refer toFIG. 9C and FIG. 9E. The vertical scaler VS 841_(—)11 starts theprocessing of Pixel_(—)1 981_(—)001, of the Top Margin 981_(—)623,identified as Row_(—)0 981_(—)300 in FIG. 9E, that is verticallyadjacent to Pixel_(—)0 911_(—)000 of the row identified as Row_(—)1981_(—)301. The video data information of both pixels are processed inaccordance with a data filtering or combining process where the dataprocessing comprises taking into consideration the number of inputpixels being processed and the vertical scaling ratio to determine theresultant video data information that is used to produce a new videodata information for a new pixel. This new pixel is the first verticallyprocessed pixel of a first vertically processed line of the verticallyprocessed output image. The first vertically processed pixel isoutputted to the inter-scaler buffer, ISB 841_(—)12 for temporarystorage. The process continues and the next two vertically adjacentpixels are then processed in a similar fashion. A second verticallyscaled pixel is then outputted to the inter-scaler buffer ISB 841_(—)12for temporary storage. The vertical scaling process continues until thelast pixel of the Top Margin 981_(—)623 is reached namely Pixel_(—)16981_(—)016. In this example, Pixel_(—)15 911_(—)015 is adjacent anddirectly below Pixel_(—)16 981_(—)016 and both pixels are the last twovertically adjacent pixels to be processed, producing the lastvertically processed pixel of the first vertically processed line of thevertically processed output image. Thus, the first vertically processedline is now complete and stored in the inter-scaler buffer ISB 841_(—)12temporary storage, which will be streamed to the horizontal scaler HS841_(—)13 upon the initiation of the horizontal scaling process for thefirst vertically scaled or processed line.

The vertical scaling process now repeats using the second line of D_(—)1981 that corresponds to Row_(—)1 981_(—)301, which is the same asRow_(—)0 911_(—)300, and the third line of D_(—)1 981 that correspondsto Row_(—)2 981_(—)302. Thus, the second vertically processed line isgenerated and outputted to the inter-scaler buffer ISB 841_(—)12 fortemporary storage. The vertical scaling process continues until theeighteenth vertically processed line of the vertically scaled outputimage is generated and outputted to the inter-scaler buffer ISB841_(—)12 for temporary storage. As the vertical scaling processoperation is being completed, then the video data information of thepixels of the topmost lines of the First Input Buffer Control 841_(—)10are no longer needed for the vertical scaling process operation of thecurrent digital image. Therefore, the topmost lines, e.g. Row_(—)0981_(—)300, Row_(—)1 981_(—)301, etc. . . . , may now be discarded, andin accordance with the design requirement one or more lines may bediscarded at a time. A first-in-first-out FIFO buffer may be used withinthe First Input Buffer Control 841_(—)10 to store the video datainformation. As the topmost line or lines are no longer needed, then theFirst Input Buffer Control 841_(—)10 may initiate a memory readoperation to retrieve a single new line or multiple lines of video datainformation to be read out of memory and into the First Input BufferControl 841_(—)10 overwriting the line or lines to be discarded. TheFirst Input Buffer Control 841_(—)10 maintains its FIFO full so that thevertical scaling process progress continuously as needed or required bythe output display module ODM_(—)1 841 and in accordance with thedesired performance of the Digital Image Processing System 800.Furthermore, the topmost line or lines of the First Input Buffer Control841_(—)10 may be kept for a certain amount of time, long enough toperform a recall or a video effect operation as may be desired ornecessary. Upon the initiation of the horizontal scaling process for thefirst vertically processed line, the horizontal scaler HS 841_(—)13retrieve the first vertically processed line from inter-scaler bufferISB 841_(—)12. The left and right margin pixels are generated for all ofthe vertically processed lines as will be described in the followingparagraphs.

In accordance with one embodiment, the generation of the video datainformation of the pixels of the Left Margin 981_(—)626 and the RightMargin 981_(—)624 is done on the fly. For example, as the video datainformation of the pixels of the vertically processed line is beingstreamed into the horizontal scaler HS 841_(—)13 from the inter-scalerbuffer ISB 841_(—)12 temporary storage. Other means for generating theLeft Margin 981_(—)626 and the Right Margin 981_(—)624 pixels may beused as well, as described earlier in this disclosure. In this example,the left margin pixel and the right margin pixel are generated using acopy of the first pixel and the last pixel of each vertically processedline, respectively. For example, the first pixel and the last pixel ofthe first vertically processed line, which is stored in the inter-scalerbuffer ISB 841_(—)12 temporary storage, are replicated to generate thetop pixel Pixel_(—)0 981_(—)000 of the Left Margin 981_(—)626 and thetop pixel Pixel_(—)117 981_(—)017 of the Right Margin 981_(—)624,respectively. In accordance with one embodiment, upon the initiation ofthe horizontal scaling process, the new vertically processed lineincluding the left and right margin pixels is streamed to the horizontalscaler HS 841_(—)13.

The horizontal scaling process is similar to the vertical scalingprocess as described above and utilize two or more horizontally adjacentpixel to generate one horizontally processed pixel. In this example, twohorizontally adjacent pixels are used to generate one horizontallyprocessed pixel. This horizontally processed pixel is streamed to theOutput Formatter 841_(—)50 for further processing. The horizontalprocessing continues until all of the horizontally processed pixels aregenerated in accordance with the desired horizontal scaling ratio.Similarly, the process continues for all the vertically processed lines,including the left and right margin pixels, and all the vertically andhorizontally processed lines are streamed to the Output Formatter841_(—)50 in the same way as for the first vertically processed line.Since we are using a scaling ratio of one in this example, thevertically and horizontally processed D_(—)1 981 comprises eighteenrows, Row_(—)0 981_(—)300 through Row_(—)17 981_(—)317 and each rowhaving a width that is equal to eighteen pixels, Width 981_(—)612 seeFIG. 9E, in accordance with Eq. 5 and Eq. 6. For example, if thevertical scaling ration is equal to one and the horizontal scaling ratiois equal to two, then the D_(—)1 Width 981_(—)612 would equal tothirty-two pixels while the D_(—)1 Height 981_(—)622 would equaleighteen pixels (or rows). The vertically and horizontally processedpixels resulting from the appended margin pixels will be appropriatelycropped by the Output Formatter 841_(—)50 so that the desired verticallyand horizontally processed pixels that correspond to the Region_(—)1 911are displayed, as will be described in the following paragraphs.

The second data path of the output display module ODM_(—)1 841independently retrieves, and processes video data information in thevertical or the horizontal directions. In this example, the UV-componentof D_(—)1 981 is independently retrieved using the Second Input BufferControl 841_(—)20. The vertical and horizontal processing is performedusing a vertical scaler VS 841_(—)21, an inter-scaler buffer ISB841_(—)22, and a horizontal scaler HS 841_(—)23. In a similar fashion asdescribed above for the first data path, the horizontal scaler HS841_(—)23 streams the vertically and horizontally processed video datainformation to the output formatter 841_(—)50.

The Output Formatter 841_(—)50 further processes and appropriatelysynchronizes and combines the vertically and horizontally processedY-component and UV-component of D_(—)1 981 to generate and output ontothe Output Display Data Path 846 the desired output image in accordancewith an output video format standard that is compatible with thedestination display region. The Output Formatter 841_(—)50 appropriatelycrops the combined vertically and horizontally processed pixels that arethe result of the appended Top Margin 981_(—)623, Bottom Margin981_(—)625, Left Margin 981_(—)626, and Right Margin 981_(—)624. Thecombined vertically and horizontally processed pixels, which are used inthe generation of the desired output image that corresponds toRegion_(—)1 911, when displayed alongside the other vertically andhorizontally processed pixels of neighboring regions will result in acontiguous and a full display a vertically and horizontally processedDigital Image 900. The Output Formatter 841_(—)50 streams or outputseach synchronized and combined vertically and horizontally processedline onto the Output Display Data Path 846, the Output Formatter841_(—)50 uses a data enable signal to indicate to an electronic displaydevice to discard or blank one or more pixels for each line. In someinstances, an entire line may be blanked. Therefore, in this examplewith a scaling ratio of one, the desired processed output image to bedisplayed that corresponds to Region_(—)1 911 comprises sixteen lines,where each line comprises sixteen pixels. The following paragraphs willdescribe a slightly different method to process or scale Region_(—)1911.

In accordance with one embodiment, the vertical and horizontalprocessing of Region_(—)1 911 of the Digital Image 900 is accomplishedby defining a quadrangle digital image D_(—)2 982 that includes all ofthe pixels of Region_(—)1 911 and a right and bottom margin pixels fromneighboring regions, as shown in FIG. 9F and FIG. 9G. In this example,it is assumed that a margin depth of one pixel is used. The right marginpixels comprise the leftmost edge pixels of Region_(—)2 912 and thetop-leftmost pixel of Region_(—)5 915. The bottom margin pixels comprisethe topmost edge pixels of Region_(—)4 914. In this example, the RightMargin 982_(—)624 is generated from the first column of pixels ofRegion_(—)2 912, comprising Pixel_(—)256 900_(—)0256 throughPixel_(—)496 900_(—)0496 in the vertical direction, and the first pixelof Region_(—)5 915, comprising Pixel 1024 900_(—)1024, see FIG. 9F. TheBottom Margin 982_(—)625 is generated from the first row of pixels ofRegion_(—)4 914, comprising Pixel_(—)768 900_(—)0768 throughPixel_(—)783 900_(—)0783 in the horizontal direction. Therefore, D_(—)2982 comprises seventeen rows, and each row comprises seventeen pixels,see FIG. 9G. The generation of top and left margin pixels for thevertical and horizontal processing of D_(—)2 982 can be done in multipleways and is illustrated in the following embodiments.

Now referring to FIG. 9H and in accordance with one embodiment, thevideo data information content of the pixels of the Top Margin982_(—)623 and the Left Margin 982_(—)626 is generated on the fly or ina similar manner as described in the embodiments above. Therefore, thequadrangle digital image D_(—)2 982 comprises eighteen rows, and eachrow comprises eighteen pixels, see FIG. 9H. The quadrangle digital imageD_(—)2 982 comprises the Bottom Margin 982_(—)625 and Right Margin982_(—)624. Thus, the vertical and horizontal processing of D_(—)2 982can be accomplished as has been described in the embodiments above. TheOutput Formatter 841_(—)50 streams or outputs each vertically andhorizontally processed line onto the Output Display Data Path 846, theOutput Formatter 841_(—)50 uses a data enable signal to indicate to anelectronic display device to discard or blank one or more pixels foreach line. In some instances, an entire line may be blanked. Therefore,in this example with a scaling ratio of one, the desired processedoutput image to be displayed that corresponds to Region_(—)1 911comprises 16 lines, where each line comprises 16 pixels. The followingparagraphs will describe a slightly different method to process or scaleRegion_(—)1 911.

Now referring to FIG. 9I and in accordance with one embodiment, thevideo data information content of the pixels of the Top Margin982_(—)623, the Bottom Margin 982_(—)695, the Left Margin 982_(—)626 andthe Right Margin 982_(—)694 are generated on the fly or in a similarmanner as described in the embodiments above. Please note that thequadrangle digital image D_(—)2 982 already comprises the Bottom Margin982_(—)625 and Right Margin 982_(—)624. Therefore, the quadrangledigital image D_(—)2 982 comprises nineteen rows, and each row comprisesnineteen pixels, see FIG. 9I. One can think of the quadrangle digitalimage D_(—)2 982 as a whole region to be processed, and the top, bottom,left and right margin are newly generated. Thus, the vertical andhorizontal processing of D_(—)2 982 can be accomplished as has beendescribed in the embodiments above. The Output Formatter 841_(—)50streams or outputs each vertically and horizontally processed line ontothe Output Display Data Path 846, the Output Formatter 841_(—)50 uses adata enable signal to indicate to an electronic display device todiscard or blank one or more pixels for each line. In some instances, anentire line may be blanked. In this example with a scaling ratio of one,the desired processed output image to be displayed, which corresponds toRegion_(—)1 911, comprises 16 lines and each line comprises 16 pixels.Accordingly, the Output Formatter 841_(—)50 processes and crops thevertically and horizontally processed pixels of D_(—)2 982 so that onlythe appropriate processed pixels that correspond to Region_(—)1 911 areused in the display of the desired output image. The Output Formatter841_(—)50 processes and crops the first line and the last two lines, andthe first column and the last two columns so that the output imagecomprises sixteen processed lines, and each processed line comprisingsixteen pixels in direct proportion the resolution of Region_(—)1 911given a vertical and horizontal scaling ratio of one. In accordance withone embodiment, the Output Formatter 841_(—)50 streams or outputs eachvertically and horizontally processed line along with a data enablesignal using the Output Display Data Path 846. The Output Formatter841_(—)50 asserts the data enable signal using appropriate timing toindicate to an electronic display module to discard or blank the firstline, the last two lines, and the first pixel and the last two pixels ofthe remaining vertically and horizontally processed lines of D_(—)2 982output image.

In accordance with one embodiment, a quadrangle digital image D_(—)3 983comprises the pixels of Region_(—)2 912, and pixels from neighboringleft, bottom, and right regions of Digital Image 900, as shown in FIG.9J. These pixels are used to create the right margin, bottom margin, andleft margin for Region_(—)2 912. In this example, the margin depth isassumed equal to one pixel. The top margin pixels are generated and thequadrangle digital image D_(—)3 983 is processed in a similar fashion asdescribed above.

In accordance with one embodiment, the quadrangle digital image D_(—)3983 comprises the pixels of Region_(—)2 912, and pixels from neighboringleft, bottom, and right regions of Digital Image 900, as shown in FIG.9J. In this example, the top, bottom, left, and right margin pixels aregenerated on the fly irrespective of whether the quadrangle digitalimage D_(—)3 983 comprises margin pixels from neighboring regions ornot. The quadrangle digital image D_(—)3 983 is processed in a similarfashion as described above and similar to the illustration forRegion_(—)1 911 as shown in FIG. 9I. In the following paragraphs, memoryaccess is described for various regions types of Digital Image 900 thatare defined using various shapes and sizes.

The Digital Image 900 is split into six regions and each region may befurther split into four sub-regions as shown in FIG. 9K. In thisexample, Region_(—)2 912 is split into four sub-regions, namelyRegion_(—)2_(—)1 912_(—)10, Region_(—)2_(—)2 912_(—)20, Region 2_(—)3912_(—)30, and Region_(—)2_(—)4 912_(—)40. In accordance with oneembodiment, an exemplary memory access request is initiated to write orread the video data information content of Region_(—)2_(—)3 912_(—)30 toor from a Second Memory Block 912_(—)30_(—)800, as shown in FIG. 9L.This exemplary memory access request is described using the commandstructure as shown in FIG. 10A. The memory locations that correspond toRegion 2_(—)3 912_(—)30 are illustrated as a shaded region enclosed bydashed lines and labeled as Second Memory Block 912_(—)30_(—)800, asshown in FIG. 9L. In this example, the Y-component of video datainformation of Region_(—)2 912 is stored within the first memory regionstarting at memory location 32 and ending at memory location 63, asshown in FIG. 9L.

In this example, a memory read command is initiated by output displaymodule ODM_(—)1 841 to retrieve the Second Memory Block 912_(—)30_(—)800that comprises the Y-component of the video data information of thepixels of Region_(—)2_(—)3 912_(—)30. The First Input Buffer Control841_(—)10 produces a memory read command comprising a Base Index 1020 toread the video data information out of Memory 850. The Base Index 1020value corresponds to the first starting memory location of the firstregion of Memory 850, and in this example equals (001)₁₀. The Region2_(—)3 912_(—)30 comprises eight memory locations, namely: 48, 50, 52,54, 56, 58, 60, and 62. The vertical and horizontal origin of theRegion_(—)2_(—)3 912_(—)30, comprising the top-leftmost pixel ofRegion_(—)2_(—)3 912_(—)30, is identified using Ystart 1030 and Xstart1040 values, respectively. In this example, the location information ofthe vertical and horizontal origin is given by Ystart 1030=(008)₁₀ thatcorresponds to the ninth row (Row_(—)8), and Xstart 1040=(002)₁₀ thatcorresponds to the third column (Col_(—)2), see Memory Location 48(Row_(—)8, Col_(—)2) 900_(—)848. Furthermore, the size information isgiven by Xcount 1060=(001)₁₀ that corresponds to one memory location inwidth or the horizontal direction, and Ycount 1050=(008)₁₀ thatcorresponds to eight memory locations in height or the verticaldirection. Therefore, the exemplary memory read command, in accordancewith the command structure of FIG. 10A, comprises the following:[Control bits], [(001)₁₀], [(008)₁₀], [(002)₁₀], [(008)₁₀], [(001)₁₀].The Memory Data Path Controller 830 generates the bases address for theintended memory region by using the Base Index 1020 value of (001)₁₀ asa pointer in a lookup table to retrieve the corresponding base address,i.e. (00001024)₁₀. The Second Memory Interface 830_(—)30 generates atleast one memory device read command using the size and locationinformation embedded within the memory read command, as has beendescribed earlier.

Now referring to FIG. 9M, the Digital Image 900 is split into sixregions, namely Region_(—)1 911, Region_(—)2 912, Region_(—)3 913,Region_(—)4 914, Region_(—)5 915, Region_(—)6 916. Region_(—)991_(—)123991_(—)123_(—)900 is a concatenation of the first row of each of theRegion_(—)1 911, Region_(—)2 912, and Region_(—)3 913. In accordancewith one embodiment, an exemplary memory access request is initiated towrite or read the video data information content of Region_(—)991_(—)123991_(—)123_(—)900 to or from a Third Memory Block 991_(—)123_(—)800, asshown in FIG. 9N. This exemplary memory access request is describedusing the command structure as shown in FIG. 10A. The memory locationsthat correspond to Region_(—)991_(—)123 991_(—)123_(—)900 areillustrated as a shaded region enclosed by dashed lines and labeled asThird Memory Block 991_(—)123_(—)800. In this example, the Y-componentof video data information of Region_(—)991_(—)123 991_(—)123_(—)900 isstored within the first memory region starting at memory location 0 andcomprising memory location 0, 1, 32, 33, 64, and 65, as shown in FIG.9N.

In this example, a memory read command is initiated by the outputdisplay module ODM_(—)1 841 to retrieve the Third Memory Block991_(—)123_(—)800, comprising the Y-component of the video datainformation of the pixels of Region_(—)991_(—)123 991_(—)123_(—)900. TheFirst Input Buffer Control 841_(—)10 produces a memory read commandcomprising a Base Index 1020 to read the video data information out ofMemory 850. The Base Index 1020 value corresponds to the first startingmemory location of the first region of Memory 850, and in this exampleequals (001)₁₀. The vertical and horizontal origin of theRegion_(—)991_(—)123 991_(—)123_(—)900, comprising the top-leftmostpixel of Region_(—)991_(—)123, is identified using Ystart 1030 andXstart 1040 values, respectively. In this example, the locationinformation is given by Ystart 1030=(000)₁₀ that corresponds to thefirst row (Row_(—)0), and Xstart 1040=(000)₁₀ that corresponds to thefirst column (Col_(—)0). Furthermore, the size information is given byXcount 1060=(006)₁₀ that corresponds to six memory location in width orthe horizontal direction, and Ycount 1050=(001)₁₀ that corresponds toone memory location in height or the vertical direction, i.e. one lineof the Digital Image 900. Therefore, the exemplary memory read command,in accordance with the structure of FIG. 10A, comprises the following:[Control bits], [(001)₁₀], [(000)₁₀], [(000)₁₀], [(001)₁₀], [(006)₁₀].The Memory Data Path Controller 830 generates the bases address for theintended memory region by using the Base Index 1020 value of (001)₁₀ asa pointer in a lookup table to retrieve the corresponding base address,i.e. (00001024)₁₀. The Second Memory Interface 830_(—)30 generates atleast one memory device read command using the size and locationinformation embedded within the memory read command, as has beendescribed above.

Now referring to FIG. 9O, the Digital Image 900 is split into sixregions, namely Region_(—)1 911, Region_(—)2 912, Region_(—)3 913,Region_(—)4 914, Region_(—)5 915, and Region_(—)6 916.Region_(—)991_(—)023 991_(—)023_(—)900 is a concatenation of Region_(—)2912, and Region_(—)3 913. In accordance with one embodiment, anexemplary memory access request is initiated to write or read the videodata information content of Region_(—)991_(—)023 991_(—)023_(—)900 to orfrom a Fourth Memory Block 991_(—)023_(—)800, as shown in FIG. 9O. Thisexemplary memory access request is similar to the memory access requestdescribed above and uses the command structure of FIG. 10A. The memorylocations that correspond to Region_(—)991_(—)023 991_(—)023_(—)900 areillustrated as a shaded region enclosed by dashed lines and labeled asFourth Memory Block 991_(—)023_(—)800. In this example, the Y-componentof video data information of Region_(—)991_(—)023 991_(—)023_(—)900 isstored within the first memory region starting at memory location 32 andends at memory location 95. The memory read command to retrieve theFourth Memory Block 991_(—)023_(—)800 is generated as has been describedin the above embodiments; see FIG. 9D as a reference for the memory sizeand location information, e.g. Ystart 1030, Xstart 1040, Ycount 1050,and Xcount 1060.

Now referring to FIG. 9P, the Digital Image 900 is split into sixregions, namely Region_(—)1 911, Region_(—)2 912, Region_(—)3 913,Region_(—)4 914, Region_(—)5 915, and Region_(—)6 916.Region_(—)991_(—)036 991_(—)036_(—)900 is a concatenation of Region_(—)3913 and Region_(—)6 916. In accordance with one embodiment, an exemplarymemory access request is initiated to write or read the video datainformation content of Region_(—)991_(—)036 991_(—)036_(—)900 to or froma Fifth Memory Block 991_(—)036_(—)800, as shown in FIG. 9P. Thisexemplary memory access request is similar to the memory access requestdescribed above and uses the command structure of FIG. 10A. The memorylocations that correspond to Region_(—)991_(—)036 991_(—)036_(—)900 areillustrated as a shaded region enclosed by dashed lines and labeled asFifth Memory Block 991_(—)036_(—)800. In this example, the Y-componentof video data information of Region_(—)991_(—)036 991_(—)036_(—)900 isstored within the first memory region starting at memory location 64through memory location 95 and memory location 160 through memorylocation 191. The memory read command to retrieve the Fifth Memory Block991_(—)036_(—)800 is generated as has been described in the aboveembodiments; see FIG. 9D as a reference for the memory size and locationinformation, e.g. Ystart 1030, Xstart 1040, Ycount 1050, and Xcount1060.

The exemplary embodiments as described in this disclosure are usedinterchangeably to develop a certain and unique Digital Image ProcessingSystem 800 that meets a widely varying input digital image processingrequirements, including various techniques to process and split an inputdigital image. Furthermore, various embodiments provide the ability tocustomize the Digital Image Processing System 800 to meet anever-changing electronic display panels' size and specification.

I claim:
 1. A method for processing video data information of an inputimage, comprising: retrieving from a memory buffer a first video datainformation that corresponds to at least a first portion of the inputimage; generating a second video data information that corresponds to atleast one pixel of one of a top margin and a bottom margin; generating athird video data information that corresponds to at least one pixel ofone of a right margin and a left margin; storing the first and secondvideo data information using a first buffer; processing the first andsecond video data information to produce a first processed video datainformation; outputting the first processed video data information to asecond buffer; storing the third video data information and the firstprocessed video data information using the second buffer; and processingthe first processed video data information and the third video datainformation to produce a second processed video data information,wherein the second processed video data information corresponds to afirst number of pixels.
 2. The method of claim 1, further comprising:generating a first data enable signal information to control displayingof a second number of pixels, wherein the second number of pixels isless than or equal to the first number of pixels; and outputting thesecond processed video data information and the first data enable signalinformation to an electronic display.
 3. The method of claim 2, furthercomprising: displaying, using a first display region of the electronicdisplay, the second number of pixels using the second processed videodata information and the first data enable signal information.
 4. Themethod of claim 1, further comprising: determining a first locationinformation of a first pixel of a quadrangle digital image, wherein thefirst location information comprises at least one of a first base indexand information corresponding to a first memory location of the memorybuffer.
 5. The method of claim 4, wherein the first video datainformation is retrieved from the memory buffer using the first locationinformation.
 6. The method of claim 4, wherein the quadrangle digitalimage comprises at least the first portion of the input image, the topmargin, the bottom margin, the left margin, and the right margin.
 7. Themethod of claim 1, wherein any one of the top margin, the bottom margin,the left margin, and the right margin comprises video data informationof at least one pixel that is generated using at least one of a videodata information corresponding to a pixel of the first portion of theinput image, a video data information corresponding to a pixel of theinput image, and a video data information corresponding to a color. 8.The method of claim 1, wherein the processing of the first and secondvideo data information to produce a first processed video datainformation includes processing in the vertical direction of at leastone pixel of the first portion of the input image and at least one pixelof one of the top margin and the bottom margin.
 9. The method of claim8, wherein the processing in the vertical direction includes scaling inthe vertical direction using a scaling value.
 10. The method of claim 1,wherein the processing of the first processed video data information andthe third video data information to produce a second processed videodata information includes processing in the horizontal direction of atleast one pixel of the first portion of the input image and at least onepixel of one of the left margin and the right margin.
 11. The method ofclaim 8, wherein processing in the horizontal direction includes scalingin the horizontal direction using a scaling value.
 12. A method forprocessing video data information of an input image, comprising:retrieving from a memory buffer a first video data information thatcorresponds to at least a first portion of the input image; generating asecond video data information that corresponds to at least one pixel ofone of a top margin and a bottom margin; generating a third video datainformation that corresponds to at least one pixel of one of a rightmargin and a left margin; processing the first and second video datainformation to produce a first processed video data information;processing the first processed video data information and the thirdvideo data information to produce a second processed video datainformation, wherein the second processed video data informationcorresponds to a first number of pixels; and storing the secondprocessed video data information using a first buffer.
 13. The method ofclaim 12, further comprising: generating a first data enable signalinformation to control displaying of a second number of pixels, whereinthe second number of pixels is less than or equal to the first number ofpixels; and outputting the second processed video data information andthe first data enable signal information to an electronic display. 14.The method of claim 13, further comprising: displaying, using a firstdisplay region of the electronic display, the second number of pixelsusing the second processed video data information and the first dataenable signal information.
 15. The method of claim 12, wherein any oneof the top margin, the bottom margin, the left margin, and the rightmargin comprises video data information of at least one pixel that isgenerated using at least one of a video data information correspondingto a pixel of the first portion of the input image, a video datainformation corresponding to a pixel of the input image, and a videodata information corresponding to a color.
 16. The method of claim 12,wherein any one of the first processed video data information and thesecond processed video data information is produced using any one of aprocessing in the vertical direction of at least one pixel of the firstportion of the input image and at least one pixel of one of the topmargin and the bottom margin, and a processing in the horizontaldirection of at least one pixel of the first portion of the input imageand at least one pixel of one of the left margin and the right margin.17. The method of claim 16, wherein the processing in the horizontaldirection includes scaling in the horizontal direction using a firstscaling value, the processing in the vertical direction includes scalingin the vertical direction using a second scaling value, and the firstscaling value corresponds to a value that is different or same as thesecond scaling value.
 18. A system to process video data information ofan input image comprising: a video memory buffer; a first memory buffer;a second memory buffer; and a first circuit that is configured to: (i)retrieve from the video memory buffer a first video data informationthat corresponds to at least a first portion of the input image, (ii)generate a second video data information that corresponds to at leastone pixel of one of a top margin and a bottom margin, (iii) store thefirst and second video data information using the first memory buffer,(iv) process the first and second video data information to produce afirst processed video data information, (v) generate a third video datainformation that corresponds to at least one pixel of one of a rightmargin and a left margin, (vi) store the third video data informationand the first processed video data information using the second buffer,and (vii) process the first processed video data information and thethird video data information to produce a second processed video datainformation, wherein the second processed video data informationcorresponds to a first number of pixels.
 19. The system of claim 18,further comprising: a second circuit that is configured to (i) generatea data enable signal to control display of a second number of pixels,and (ii) output the second processed video data information and the dataenable signal, wherein the second number of pixels is less than or equalto the first number of pixels.
 20. The system of claim 19, furthercomprising: a display device having at least a first and second displayregions, the display device includes a third circuit that is configuredto (i) receive the second processed video data information and the dataenable signal, and (ii) display the second number of pixels using afirst region of the display device, wherein the third circuit controlsthe display of the second number of pixels using the data enable signal.21. The system of claim 18, wherein any one of the top margin, thebottom margin, the left margin, and the right margin comprises videodata information of at least one pixel that is generated using at leastone of a video data information corresponding to a pixel of the firstportion of the input image, a video data information corresponding to apixel of the input image, and a video data information corresponding toa color.
 22. The system of claim 18, wherein the first circuit isfurther configured to produce the first processed video data informationby processing in the vertical direction at least one pixel of the firstportion of the input image and at least one pixel of one of the topmargin and the bottom margin.
 23. The system of claim 18, wherein thefirst circuit is further configured to scale, in the vertical direction,the first processed video data information using a scaling value. 24.The system of claim 18, wherein the first circuit is further configuredto produce the second processed video data information by processing inthe horizontal direction at least one pixel of the first portion of theinput image and at least one pixel of one of the left margin and theright margin.
 25. The system of claim 18, wherein the first circuit isfurther configured to scale, in the horizontal direction, the secondprocessed video data information using a scaling value.
 26. The systemof claim 18, wherein the first circuit comprises at least one of a logiccircuit, a central processing unit (CPU), a software, and a firmware.27. The system of claim 26, wherein the first circuit is programmed toperform one or more of the first circuit configurations (i) to (vii).